A
Adam William Saxler
Researcher at Cree Inc.
Publications - 170
Citations - 6832
Adam William Saxler is an academic researcher from Cree Inc.. The author has contributed to research in topics: Layer (electronics) & Nitride. The author has an hindex of 44, co-authored 170 publications receiving 6634 citations. Previous affiliations of Adam William Saxler include Northwestern University & Micron Technology.
Papers
More filters
Journal ArticleDOI
30-W/mm GaN HEMTs by field plate optimization
Yifeng Wu,Adam William Saxler,Marcia Moore,R.P. Smith,Scott Sheppard,P. Chavarkar,T. Wisleder,Umesh K. Mishra,P. Parikh +8 more
TL;DR: In this article, a GaN high-electron-mobility-transistors (HEMTs) on SiC were fabricated with field plates of various dimensions for optimum performance, and an enhancement in radio frequency (RF) current-voltage swings was achieved with acceptable compromise in gain, through both reduction in the trapping effect and increase in breakdown voltages.
Journal ArticleDOI
Heavy doping effects in Mg-doped GaN
Peter Kozodoy,Huili Xing,Steven P. DenBaars,Umesh K. Mishra,Adam William Saxler,R. Perrin,Said Elhamri,W. C. Mitchel +7 more
TL;DR: In this paper, the electrical properties of p-type Mg-doped GaN were investigated through variable-temperature Hall effect measurements, and the measured doping efficiency drops in samples with Mg concentration above 2×1020 cm−3.
Proceedings ArticleDOI
40-W/mm Double Field-plated GaN HEMTs
TL;DR: In this paper, a double field-plated GaN HEMT with increased power density and robustness was presented, where a first field plate (FP1) was integrated with the gate for both reduced gate resistance and elimination of electron trapping.
Patent
Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
TL;DR: In this paper, a mask is fabricated and patterned on the first cap layer, and a second cap layer comprising a Group III-nitride semiconductor material is selectively fabricated using the patterned mask.
Patent
Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors
TL;DR: In this paper, the authors proposed a method of fabricating a Group III-nitride-based heterojunction transistor, which includes a substrate and a first Group III nitride layer, such as an AlGaN-based layer, on the substrate.