Worldwide commercial interest in carbon nanotubes (CNTs) is reflected in a production capacity that presently exceeds several thousand tons per year. Currently, bulk CNT powders are incorporated in diverse commercial products ranging from rechargeable batteries, automotive parts, and sporting goods to boat hulls and water filters. Advances in CNT synthesis, purification, and chemical modification are enabling integration of CNTs in thin-film electronics and large-area coatings. Although not yet providing compelling mechanical strength or electrical or thermal conductivities for many applications, CNT yarns and sheets already have promising performance for applications including supercapacitors, actuators, and lightweight electromagnetic shields.

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Carbon Nanotubes: Present and Future Commercial Applications

Electron and ambipolar transport in organic field-effect transistors.

5. In Situ Polymerization 3907 5.1. General Polymerization 3907 5.2. Photopolymerization 3910 5.3. Surface-Initiated Polymerization 3912 5.4. Other Methods 3913 6. Colloidal Nanocomposites 3913 6.1. Sol-Gel Process 3914 6.2. In Situ Polymerization 3916 6.2.1. Emulsion Polymerization 3917 6.2.2. Emulsifier-Free Emulsion Polymerization 3919 6.2.3. Miniemulsion Polymerization 3920 6.2.4. Dispersion Polymerization 3921 6.2.5. Other Polymerization Methods 3923 6.2.6. Conducting Nanocomposites 3924 6.3. Self Assembly 3926 7. Other Preparative Methods 3926 8. Characterization and Properties 3928 8.1. Chemical Structure 3928 8.2. Microstructure and Morphology 3929 8.3. Mechanical Properties 3933 8.3.1. Tensile, Impact, and Flexural Properties 3933 8.3.2. Hardness 3936 8.3.3. Fracture Toughness 3937 8.3.4. Friction and Wear Properties 3937 8.4. Thermal Properties 3938 8.5. Flame-Retardant Properties 3941 8.6. Optical Properties 3942 8.7. Gas Transport Properties 3943 8.8. Rheological Properties 3945 8.9. Electrical Properties 3945 8.10. Other Characterization Techniques 3946 9. Applications 3947 9.1. Coatings 3947 9.2. Proton Exchange Membranes 3948 9.3. Pervaporation Membranes 3948 9.4. Encapsulation of Organic Light-Emitting Devices 3948

Polymer/Silica Nanocomposites: Preparation, Characterization, Properties, and Applications

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

https://cyberleninka.org/article/n/247805.pdf

A brief review of atomic layer deposition: from fundamentals to applications

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

Sub-10 nm carbon nanotube transistor.

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Electromigration in on-chip Cu interconnections with a selective electroless metal coating, CoWP, CoSnP, or Pd, on the top surface of Cu damascene lines has been investigated. The 10–20 nm thick metal cap significantly improves electromigration lifetime by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure by electromigration.

Reduced electromigration of Cu wires by surface coating

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneou...

Lynne Gignac

Papers

Sub-10 nm carbon nanotube transistor.

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Reduced electromigration of Cu wires by surface coating

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si