An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material being contained within the interconnect opening and with a top surface of the conductive fill material within the interconnect opening being exposed. A capping material is formed on the top surface of the conductive fill material, and the capping material is an amorphous alloy or is a microcrystalline alloy having stuffed grain boundaries. A thermal curing process is then performed for curing the low-K precursor material to become a porous low-K dielectric material. The capping material on the top surface of the conductive fill material is impervious to at least one of oxygen, carbon, hydrogen, chlorine, and porogen fragments that are generated as out-gassing volatile by-products from the low-K precursor material during the thermal curing process to preserve the integrity of the interconnect structure. In another aspect for fabricating an interconnect structure, an interconnect opening is formed within a porous dielectric material with opened pores at sidewalls of the interconnect opening. A diffusion barrier material is formed at a bottom wall of the interconnect opening. The diffusion barrier material is then sputtered away from the bottom wall of the interconnect opening and onto the sidewalls of the interconnect opening to substantially fill the opened pores at the sidewalls with the diffusion barrier material. The interconnect opening is then filled with a conductive fill material after the opened pores at the sidewalls of the interconnect opening are filled with the diffusion barrier material.

Interconnect structure formed in porous dielectric material with minimized degradation and electromigration

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

Reliability challenges for copper interconnects

As the dimensions of conductors shrink into the nanoscale, their electrical conductivity becomes dependent on their size even at room temperature. Although the behavior varies dramatically as temperatures increase from nanokelvins to hundreds of kelvins, the effect is generally to increase the resistivity above that of bulk material. As such, the underlying size-dependent phenomena have become increasingly important as advanced technologies have shifted their focus first from macro- to microscale and more recently from micro- to nanoscale dimensions. Indeed, the size-dependent increase of electrical resistivity that results from electron scattering on external and internal surfaces of copper conductors has already become technology limiting in modern microelectronics. This article summarizes the phenomena that underlie size effects, focusing on conduction in copper lines in particular. Attention is given to describing key innovations in both theoretical and experimental assessments that have significantly...

Size-Dependent Resistivity in Nanoscale Interconnects

Electromigration in on-chip Cu interconnections with a selective electroless metal coating, CoWP, CoSnP, or Pd, on the top surface of Cu damascene lines has been investigated. The 10–20 nm thick metal cap significantly improves electromigration lifetime by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure by electromigration.

Reduced electromigration of Cu wires by surface coating

A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

Method for forming Co-W-P-Au films

Reduced Cu interface diffusion by CoWP surface coating

An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Copper recess process with application to selective capping and electroless plating

Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

Judith M. Rubino

Papers

Reduced electromigration of Cu wires by surface coating

Method for forming Co-W-P-Au films

Reduced Cu interface diffusion by CoWP surface coating

Copper recess process with application to selective capping and electroless plating

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects