B
B.A. Bloechel
Researcher at Intel
Publications - 4
Citations - 746
B.A. Bloechel is an academic researcher from Intel. The author has contributed to research in topics: CMOS & Voltage regulator. The author has an hindex of 4, co-authored 4 publications receiving 707 citations.
Papers
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Journal ArticleDOI
Area-efficient linear regulator with ultra-fast load regulation
TL;DR: In this article, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mV/sub P-P/output droop with only a small on-chip decoupling capacitor of 0.6 nF.
Proceedings ArticleDOI
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
Ali Keshavarzi,S. Ma,Siva G. Narendra,B.A. Bloechel,Kaizad Mistry,Tahir Ghani,S. Borkar,Vivek De +7 more
TL;DR: It is shown that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V/sub t/ at both high and room temperatures, especially when target intrinsic leakage currents are high.
Journal ArticleDOI
5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS
Sriram R. Vangal,Mark A. Anders,Nitin Borkar,E. Seligman,V. Govindarajulu,Vasantha Erraguntla,H. Wilson,Amaresh Pangal,V. Veeramachaneni,James W. Tschanz,Y. Ye,Dinesh Somasekhar,B.A. Bloechel,G. Dermer,Ram Krishnamurthy,Krishnamurthy Soumyanath,Sanu Mathew,Siva G. Narendra,M.R. Stan,S. Thompson,Vivek De,S. Borkar +21 more
TL;DR: A 32 b integer execution core implements 12 instructions and circuit and body bias techniques together increase the core clock frequency to 5 GHz, in a 130 nm six-metal dual-V/sub T/ CMOS process.
Proceedings Article
Area-efficient linear regulator with ultra-fast load regulation
TL;DR: In this paper, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mVp-p output droop for a 100mA load step with only a small on-chip decoupling capacitor of 0.6 nF.