Recent Advances in GaN‐Based Power HEMT Devices

A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A new lateral power MOSFET structure [folded-accumulation LDMOS (FALDMOS)] is proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majority-carrier accumulation layer is formed as the device is in on state due to the extended gate in the drift region whose concentration is higher than that in a conventional LDMOS at the same breakdown voltage (BV), resulting from the additional electric-field modulation, and an extra majority carrier is introduced on the sidewall of the trench, which reduced the on-resistance of the drift region further. In addition, the channel density is doubled because of trenching the folded channel, which reduced the channel on-resistance. It indicates by simulation that the specific on-resistance of 4.6 mOmegamiddotmm2 with a BV of 27.4 V in FALDMOS is lower than that of the previously reported lowest one.

Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance Ron,sp is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage Bv. In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces Ron,sp of the drift region. This indicates that the ideal silicon limit of the tradeoff of Bv and Ron,sp has been broken due to the lowest Ron,sp value in the proposed MOSFET. In the proposed MOSFET, Ron,sp (i.e., 13.5 mΩ·cm2) and Bv (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an Ron,sp of 26 mΩ·cm2 and Bv of 400 V) and a superjunction structure (i.e., with an Ron,sp of 98 mΩ·cm2 and Bv of 410 V).

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

A new superjunction lateral double diffused MOSFET (LDMOST) is designed with an N-type buried layer in the P-substrate near the drain to suppress the effect of substrate-assisted depletion resulting from N-type charges' compensating charges' imbalance between the pillars of the superjunction layer. By the effect of the electric field modulation, a more uniform surface electric field is obtained by the new high electric field peak introduced by the p-n junction of the P -substrate and N-type charges' compensation layer. The new effect of reduced bulk field is introduced to improve the vertical breakdown voltage (BV) by reducing the high bulk electric field around the drain. Fabricated N-buried SJ LDMOST with a drift region length of 35 mum and a pillar width of 4.0 mum exhibits a specific on resistance of 98 mOmegamiddotcm2 and a BV of 410 V.

New Superjunction LDMOS With $N$ -Type Charges' Compensation Layer

A new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed in this letter, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF). The SIPOS SJ-LDMOS along the three dimensions are subject to the electric field modulation, which achieves the complete 3D-RESURF effect. The simulated breakdown voltage (BV) for the unit length of the drift region is improved to 19.4 $\mathrm {V}/ \mu \text{m}$ . The drift region with the high concentration compared with the conventional LDMOS can be depleted completely in the OFF-state to obtain the high BV. Moreover, the majority carrier accumulation can be formed to further decrease $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ (specific on resistance) during the ON-state operation. Three effects have been combined to SIPOS SJ-LDMOS for the superjunction ideal, electric field modulation and the majority carrier accumulation by SIPOS. The tradeoff between the BV and $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ has been improved to break through the silicon limit. The results show that the experimental $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ of SIPOS SJ-LDMOS is 18 $\text{m}\Omega \cdot \textrm {cm}^{2}$ with the tested BV of 376 V, which is less than that of 31.1 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the $N$ -buffer SJ-LDMOS with the simulated BV of 287 V, and far less than 71.8 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the conventional LDMOS with the simulated BV of 254 V for the same drift region length of 20 $\mu \text{m}$ .

Baoxing Duan

Papers

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

New Superjunction LDMOS With $N$ -Type Charges' Compensation Layer

Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

Complete 3D-Reduced Surface Field Superjunction Lateral Double-Diffused MOSFET Breaking Silicon Limit