An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

Silicides and ohmic contacts

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Radiation effects in SOI technologies

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

The threshold voltage, V/sub th/, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V/sub th/ roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, /spl Delta/V/sub th/ is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V/sub th/ design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V/sub th/ design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained. >

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFET's with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFET's are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits. >

Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits

Fully depleted SOI MOSFET's include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentration's dependence on drain voltage. >

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Viral lower respiratory tract infections (LRTIs) are an underappreciated cause of critical illness in adults. Recent advances in viral detection techniques over the past decade have demonstrated viral LRTIs are associated with rates of morbidity, mortality, and health care utilization comparable to those of seen with bacterial community acquired and nosocomial pneumonias. In this review, we describe the relationship between viral LRTIs and critical illness, as well as discuss relevant clinical features and management strategies for the more prevalent respiratory viral pathogens.

https://journals.sagepub.com/doi/pdf/10.1177/0885066615585944

C.T. Nguyen

Papers

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Viral Respiratory Infections of Adults in the Intensive Care Unit