The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

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Metrology for the next generation of semiconductor devices

In semiconductor manufacturing processes, run-to-run (R2R) control is used to improve productivity by adjusting process inputs run by run. A process will be controlled based on information obtained during or after a process, including metrology values of wafers. Those metrology values, however, are usually available for only a small fraction of sampled wafers. In order to overcome the limitation, one can use virtual metrology (VM) to predict metrology values of all wafers, based on sensor data from production equipments and actual metrology values of sampled wafers. In this paper, we develop VM prediction models using various data mining techniques. We also develop a VM embedded R2R control system using the exponentially weighted moving average (EWMA) scheme. The experiments consist of two parts: (1) verifying VM prediction models with actual production equipments data, and (2) conducting simulations of the R2R control system. Our VM prediction models are found to be accurate enough to be directly implemented in actual manufacturing processes. The simulation results show that the VM embedded R2R control system improves productivity.

Virtual metrology for run-to-run control in semiconductor manufacturing

Scanning electron microscope measurement of width and shape of 10 nm patterned lines using a JMONSEL-modeled library

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

State of the Art and Future Perspectives in Advanced CMOS Technology.

This paper will examine the future for critical dimension (CD) metrology. First, we will present the extensive list of applications for which CD metrology solutions are needed, showing commonalities and differences among the various applications. We will then report on the expected technical limits of the metrology solutions currently being investigated by SEMATECH and others in the industry to address the metrology challenges of future nodes, including conventional CD scanning electron microscopy (CD-SEM) and optical critical dimension (OCD) metrology and new potential solutions such as He-ion microscopy (HeIM, sometimes elsewhere referred to as HIM), CD atomic force microscopy (CD-AFM), CD small-angle x-ray scattering (CD-SAXS), high-voltage scanning electron microscopy (HV-SEM), and other types. A technical gap analysis matrix will then be demonstrated, showing the current state of understanding of the future of the CD metrology space.

Gaps analysis for CD metrology beyond the 22nm node

Shrinking design rules and reduced process tolerances require tight control of CD linewidth, feature shape, and profile of
the printed geometry. The Holistic Metrology approach consists of utilizing all available information from different
sources like data from other toolsets, multiple optical channels, multiple targets, etc. to optimize metrology recipe and
improve measurement performance. Various in-line critical dimension (CD) metrology toolsets like Scatterometry OCD
(Optical CD), CD-SEM (CD Scanning Electron Microscope) and CD-AFM (CD Atomic Force Microscope) are typically
utilized individually in fabs. Each of these toolsets has its own set of limitations that are intrinsic to specific
measurement technique and algorithm. Here we define "Hybrid Metrology" to be the use of any two or more metrology
toolsets in combination to measure the same dataset. We demonstrate the benefits of the Hybrid Metrology on two test
structures: 22nm node Gate Develop Inspect (DI) & 32nm node FinFET Gate Final Inspect (FI). We will cover
measurement results obtained using typical BKM as well as those obtained by utilizing the Hybrid Metrology approach.
Measurement performance will be compared using standard metrology metrics for example accuracy and precision.

A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM

The International Technology Roadmap for Semiconductors (ITRS) provides a set of Metrology specifications as targets for each technology node. In the current edition (2007) of the ITRS the conventional precision (reproducibility) is replaced with a new metric - measurement uncertainty for dimensional metrology 1 . This measurement uncertainty contains single tool precision, tool-to-tool matching, sampling uncertainty, and inaccuracy (sample-to-sample bias variation and other effects). Clearly, sampling uncertainty is a major component of measurement uncertainty. This paper elaborates on sampling uncertainty and provides statistical estimates for sampling uncertainty. The authors in this paper address the importance and the methods of proper sampling. The correct sampling captures and allows for the expression of the information needed for adequate patterning process control. Along with typical manufacturing process control cases (excursion control, advanced and statistical process control), several other applications are explored such as optical and electron beam line width measurement calibration, measurement tool evaluations, lithographic scanner assessment and optical proximity correction implementation. The authors show how appropriate choices among measurement techniques, sampling methods, and interpretation of measurement results give meaningful information for process control and demonstrate how an incorrect choice can lead to wrong conclusions.

Impact of sampling on uncertainty: semiconductor dimensional metrology applications

The conventional premise, long-touted among the semiconductor processing community, that metrology is a ldquonon-value-added necessary evil,rdquo is a misleading and dangerous assertion, which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled ldquovalue-addedrdquo processing steps in lithography and etch, such that they can be considered integral parts of the processes. Various key trends in modern, state-of-the-art processing such as optical proximity correction, design for manufacturability, and advanced process control are based, at their hearts, on the assumption of fine-tuned metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities to create value through the engineering of tight and targetable process distributions. Such distributions make possible predictability in speed-sorts and in other parameters, which results in a high-end product. Additionally, significant reliance has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology team using quality practices. This paper will explore the relationships among present and future trends and challenges in metrology, including equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology will be demonstrated to have shifted to being a ldquokey enabler of large revenues,rdquo debunking the out-of-date premise that metrology is ldquonon-value-added.rdquo

Value-Added Metrology

The need for 3D metrology is becoming more urgent to address critical gaps in metrology for both lithographic and etch
processes. Current generation lithographic processing (ArF source, where λ=193 nm) sometimes results in photoresist
lines with re-entrant profiles or T-topping, as do many etch processes. A re-entrant profile misleads top-down metrology
into reading the critical dimension (CD) as too large. Recent advances in gate process technology also raise challenges to
traditional top-down metrology. One such example is the FinFET, which is truly a 3D device with 3D metrology needs.
The ability to measure the bottom width of a profile is crucial for process control. Recently, tilt-beam critical dimension-scanning
electron microscopy (CD-SEM) applications have been developed to measure the bottom CD of such features,
using the tilted-view to "see" the bottom, avoiding the feature's larger top. This is an important achievement, as the
bottom of a profile is the main feature of interest in many processes.
Estimation of sidewall angle (SWA) is also important. For several years, tilt-beam CD-SEM has been an available
technique for this measurement, with limited adoption by the litho-metrology community. However, in this paper we
will explore another method to use the tilt feature to measure average sidewall angle, based on edgewidth measurement
and the assumption of basic trapezoidal profile and known height and combined with the ability to sample multiple-features.
While it will not provide exact profile shape, this technique can be quite useful in providing average profile
information and will definitely exhibit good throughput. Samples used will be photoresist and etched FinFET structures
to measure sidewall angles. Correlations of the results to a traceable CD-atomic force microscopy (AFM) reference
measurement system are provided. Conclusions will show preliminary findings of the readiness of tilt-beam CD-SEM
for measuring profile and, by extension, the status of measuring 3D structures such as FinFETs, and using CD-SEM as a
direct control of lithographic tooling for T-topped photoresist profiles.

The coming of age of tilt CD-SEM

The trend of reducing the feature size in ICs requires tightening control of critical dimension (CD) variability for optimal
device performance. This drives a need to be able to accurately characterize the variability in order to have reliable
metrics to drive improvement in development. Variation in CDs can come from various sectors such as mask, OPC,
litho & Etch. Metrology is involved in all sectors and it is important to understand the accuracy limitations in metrology
contributing to CD variability. Inaccuracy of the CD-SEM algorithm arising from profile variations is one example.
Profile variation can result from process and design variation. Total Measurement Uncertainty (TMU) is a metric
dependent on the precision of tool under test (CD-SEM here) and relative accuracy, and can track the accuracy of CD
measurements in the presence of varying profiles. This study explores metrology limitations to capture the design and
process contributions to the CD variation at the post litho step. In this paper lithography scanner focus-exposure matrix
wafer was used to capture the process variation. CD and profile data is taken from varying focus fields. The sample
plan described in this paper also covers the design variation by including nested features and isolated features of various
sizes. Appropriate averaging methodology has been adopted in an attempt to decouple the process and design related
CD variation to TMU. While the tool precision can be suppressed by sufficient averaging, the relative accuracy cannot.
This relative accuracy is affected by the complex CD-SEM probe to sample interactions and sensitivity of CD-SEM
algorithms to different feature profiles. One consequence of this is the average offsets between physical CDs (CDAFM)
and SEM CDs change significantly with the defocus. TMU worsens as the focus range is increased from nominal
focus. This paper explores why this is so and also discusses the challenges for the CD-AFM to accurately measure
complex and varying profiles. There is a discussion of the implications of this study for the production measurement
uncertainty, OPC calibration measurement at process of record conditions, and for process window OPC. Results for
optimizing the CD-SEM algorithm to achieve superior accuracy across both design and process induced variation will
also be presented.

Chas Archie

Papers

A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM

Impact of sampling on uncertainty: semiconductor dimensional metrology applications

Value-Added Metrology

The coming of age of tilt CD-SEM

The measurement uncertainty challenge of advanced patterning development