Showing papers by "Chenming Hu published in 1989"

Temperature acceleration of time-dependent dielectric breakdown

Abstract: A model is proposed for predicting the temperature dependence of time-to-breakdown t/sub BD/ in MOS circuits. While a previous study proposed a field-dependent activation energy, this model predicts that the activation energy for t/sub BD/ is dependent on both the oxide quality and the applied field. This explains the wide range of activation energies reported in the literature. The modeling of the activation energy and temperature acceleration factor as a function of t/sub BD/ is introduced in order to compare test results from different oxide technologies. The activation energy is found to increase with the breakdown time. This model provides good estimates of oxide lifetime for voltages down to 5 V and for temperatures between 25 and 150 degrees C. On the basis of the proposed model, an oxide with a lifetime of 1000 years at 25 degrees C is expected to last 47 years at 75 degrees C and 4.8 years at 125 degrees C. >

Electromigration interconnect lifetime under AC and pulse DC stress

Abstract: A vacancy relaxation model which predicts the DC lifetime, pulse DC lifetime, and AC lifetime for all waveforms and all frequencies above 10 kHz is proposed. The AC lifetimes of aluminum interconnect are experimentally found to be more than 10/sup 3/ times larger than DC lifetime at the same current density. AC stress lifetimes have the same dependences on current magnitude and temperature, for T >

High voltage power IC process

Abstract: A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.

Hot-carrier-induced degradation of metal-oxide-semiconductor field-effect transistors: Oxide charge versus interface traps

Abstract: Whether hot‐carrier‐induced degradation of metal‐oxide‐semiconductor field‐effect transistors is caused by charge trapping in the oxide or interface‐trap generation is a subject of considerable interest. We show that both processes take place in the hot‐carrier‐induced degradation. The relative importance of the two mechanisms depends on the stressing condition and the electron‐trap density in the oxide. Charge trapping may be a dominant mechanism for devices with high trap density in the gate oxide. When subjected to severe degradation either by very‐high‐voltage stressing or by long‐term stressing, the degradation of n‐channel transistors seems to be mostly due to charge trapping as a result of oxide‐trap generation by channel hot electrons. Under pulse stress, if the gate voltage turns off in the presence of high drain voltage, the ratio of charge trapping to interface‐trap generation appears to be larger than under dc stress. This may be due to the generation of oxide traps by electron‐hole recombination in the oxide. For a normal good oxide fabricated in the state‐of‐the‐art technology under the worst‐case dc bias condition or under pulse stress with inverterlike waveforms, hot‐electron trapping contributes less than 10% to the device degradation and interface‐trap generation is the dominant mechanism of device degradation.

Circuit reliability simulator-oxide breakdown module

Abstract: A computer program which generates statistics about circuit failures due to MOS oxide breakdown has been developed The program, CORS (Circuit Oxide Reliability Simulator), predicts the probability of circuit failure as a function of operating time, temperature, power supply voltage, and input waveforms It consists of a preprocessor and postprocessor for SPICE CORS calculates the probability of failure by using the node voltages provided by SPICE and oxide defect statistics provided by the user The effect of burn-in on oxide reliability can also be simulated CORS is linked to a hot electron and an electromigration reliability simulator Simulation results are presented >

Effects of self-heating on integrated circuit metallization lifetimes

Abstract: The authors present simulation results, an experimental technique, and a model for estimating the temperature rise and time-to-failure (TTF) of interconnect They introduce the concept of derating factor for electromigration TTF due to self-heating The derating factor is the factor by which the lifetime is reduced by temperature rise in the interconnect It is shown that in the limit of high frequencies, the temperature rise can be estimated in a straightforward manner using the root-mean-square current density after the thermal resistance of the structure has been determined from DC measurements The implication of the temperature dependence on J/sub rms/ for the usually quoted J/sub ave/ design rule was examined It was determined that self-heating is probably not significant for the usual design rule average current density of 1*10/sup 5/ A/cm/sup 2/ for operation at frequencies >10 MHz and duty factors >01% However, if the design rule is increased to 1*10/sup 6/ A/cm/sup 2/, self-heating might become significant >

Gate current in OFF-state MOSFET

Abstract: The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-AA or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I/sub D/ walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure. >

Internal ESD transients in input protection circuits

Abstract: The operation of a popular thick-field-device/grounded-gate transistor combination input protection circuit under electrostatic-discharge (ESD) stress is studied using a special test circuit. By monitoring internal voltages and currents, it was possible to observe how each element in the protection circuit contributed to the overall ESD protection. By means of the special test circuit it was determined that no degradation of the first gate-oxide transistor took place under ESD stress. >

p-MOSFET gate current and device degradation

Abstract: Hot-carrier-limited device lifetime of surface-channel p-MOSFETs is found to correlate well with gate current over a wide range of bias. The same result is not observed for buried-channel p-MOSFETs. A gate current model for surface-channel p-MOSFETs is presented. Using this gate current model, reasonable estimates of AC stress lifetime can be made based on DC stress data. >

Correlation between channel hot-electron degradation and radiation-induced interface trapping in MOS devices

Abstract: A correlation between channel hot-carrier induced degradation is conventional-drain NMOSFETS and radiation-induced transconductance (g/sub m/) degradation is described. The device lifetime, tau /sub HE/, was proportional to the 1.5 power D)/sub EFF/, where D/sub EFF/ is the radiation dose when Delta g/sub m//g/sub m/=0.5. These results indicate that radiation-induced interface trapping is a strong indicator of hot-electron-device lifetime. The proposed radiation test can be applied to devices with both radiation-hard and radiation-soft field oxide. Initial results on lightly-doped-drain (LDD) devices indicate that correlation between hot-electron degradation and radiation-induced interface trapping is strongly dependent on the design of the LDD. >

P-MOSFET gate current and device degradation

Abstract: Hot-carrier-limited device lifetime of surface-channel p-MOSFETs (p-channel metal-oxide-semiconductor field-effect transistors) is found to correlate well with gate current over a wide range of bias. The same result is not observed for buried-channel p-MOSFETs. A gate current model for surface-channel p-MOSFETs is presented. Using this gate current model, reasonable estimates of AC (pulse) stress lifetime can be made based on DC stress data. >

A 30 mips vlsi cpu

Abstract: A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown. >

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Abstract: Hot-electron degradation in deep-submicrometer MOSFETs at 3.3 V and below is studied. Using a device with L/sub eff/=0.1 mu m and T/sub ox/=75 AA, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO/sub 2/ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power-supply voltage to insure a 10-yr device lifetime without using LDD (lightly doped drains) is determined as a function of channel length (down to 0.1 mu m) and oxide thickness. >

Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits

Abstract: A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be utilized in a circuit simulator to evaluate integrated-circuit designs and aid in the provision of adequate upset margins for various operating environments. Additional subcircuit construction is unnecessary since the electrical responses to the different phenomena are intrinsic to the device template. Example simulations using SPICE3 are described

The effects of off-axis substrate orientation on MOSFET characteristics

Abstract: The effects of off-axis substrate orientation on MOSFET performance and reliability are examined As the wafer is tilted off-axis around the axis, two principal effects are observed First, for current flow normal to the axis of rotation, inversion-layer mobility is lower than for current flow in the parallel direction This mobility difference is due to anisotropy in the inversion-layer effective mass as well as increased surface roughness in the normal direction Second, because surface roughness enhances nonuniform oxidation, thin spots in the gate oxide are generated which increase the susceptibility of the gate oxide to defect-related failure The performance anisotropy may possibly be alleviated by rotating substrates in the direction, such that the normal and parallel directions possess equivalent inversion-layer effective mass and degrees of surface roughness The oxide quality may possibly be improved by using a two-step oxidation procedure, where an intermediate high-temperature anneal is used to smooth the oxide >

A two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM

Abstract: Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. A structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti/Al(2.5%Cu)/Si metal lines patterned by reactive ion etching. This structure has been successfully implemented both on BEOL test sites and in device runs to fabricate a selectively scaled 0.5- mu m-channel-length 64-kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal to or better than that achieved with metal lift-off processing. Functional testing of the 64-kb SRAM produced many chips with better than 90% yield, which is also equal to or better than that achieved with a nonplanarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2. No degradation of device characteristics due to the BEOL processing could be detected. >

Hot-carrier effects in depletion-mode MOSFETs

Abstract: Under the same gate and drain bias, the substrate current in a depletion-mode MOSFET is smaller than in an enhancement-mode MOSFET. The difference, however, is gate bias dependent, being larger at low gate voltages and smaller at high gate bias. The phenomenon can be understood in terms of an effective gate-oxide thickness concept. Other hot-carrier effects in the depletion-mode MOSFET, such as gate current and hot-carrier-induced breakdown, can also be understood on the same basis. On the other hand, hole injection into the oxide at very low V G is larger in a depletion-mode device. Such large hole injection leads to a more negative V t after stressing. The maximum shift in V t (negative ΔV t ) is comparable to that in an enhancement-mode device.

GaAs MESFET model for circuit simulation

Abstract: This paper describes a generalized circuit model for GaAs MESFETs. The novel features of the model include continuous descriptions for the intrinsic FET, Schottky diode and inter-electrode capacitance, valid both above and below device threshold. The model also displays good agreement with HEMT characteristics.

Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates

Abstract: A calculation of the channel-substrate space charge densities and dimensions is required in the formulation of device models for modern GaAs FETs which are fabricated on semi-insulating substrates with multiple deep levels. We describe a procedure to deduce this information from the compensation scheme utilized to obtain semi-insulating behavior.

Interfacial charge modification between SiO2 and silicon

Abstract: A positive flatband voltage shift, ΔVfb ≂+0.4 V, with respect to unimplanted portions of the same wafer, was obtained when calcium (1×1013 cm−2) was implanted into 87 nm of thermally grown oxide on an n‐type 〈100〉 substrate and annealed. Calcium acts as a low‐efficiency n‐type dopant in silicon (<0.1% activated) which eliminates the possibility of calcium interactions in the substrate causing the flatband behavior. Calcium profiles after a 1100 °C anneal show considerable loss from the oxide but also indicate occurrence of stable sites in the SiO2 region near the oxide‐silicon interface. Theoretical calculations on a model SiO2 structure predict an effective negative charge at the Si/SiO2 interface due to calcium incorporation in agreement with the general behavior observed experimentally; moreover, the calculations predict that aluminum and strontium will behave in a similar fashion to calcium when implanted into SiO2 while boron will not.