A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

This paper presents a diagnosis methodology able to improve the diagnosis resolution by considering only the logic information provided by the tester. The main advantage of the outlined methodology is the capability to deal with several fault models at a time, both static and dynamic, setting up a unified framework for logic diagnosis able to manage also transistor level faults. Experiments on ITC'99 benchmark circuits show the efficiency of the proposed method both in terms of diagnosis resolution and required CPU time.

Improved Diagnosis Resolution without Physical Information

This paper presents an extended version of a diagnosis method proposed so far, that considers only the logic information provided by the tester to achieve diagnosis results. The main advantage of the proposed method is its capability to handle several fault models at the same time, e.g., static, dynamic, at transistor level, thus setting up a unified framework for logic diagnosis. Experiments on ITC'99 benchmark circuits show the efficiency of the proposed method both in terms of diagnosis resolution and required CPU time.

Improving Diagnosis Resolution without Physical Information

Fault diagnosis is important in improving the design process and the manufacturing yield of nanometer circuits. It is however a challenging problem as today's complex defects lead to an explosion of the diagnosis solution space with the increasing number of possible fault locations and fault models. Our goal in this study consists in developing a new diagnosis method targeting almost all the nanometer defects in an unified manner (stuck-at, delay, open, stuck-on/open, short, resistive opens or shorts). The context of this study can be either external scan testing or scan-based BIST where time or space compaction is normally applied to test responses. Only logic cores are assumed as circuit under test/diagnosis in this study.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00136869/document

Unified Diagnostic Method Targeting Several Fault Models

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.

Christian Landrault

Papers

Improved Diagnosis Resolution without Physical Information

Improving Diagnosis Resolution without Physical Information

Unified Diagnostic Method Targeting Several Fault Models

A Unified DFT Approach for BIST and External Test

Embedded Flash Testing