A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

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Slow write driver faults in 65nm SRAM technology: analysis and March test solution

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan technology increases the switching activity well beyond that of the functional operation of an IC In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (ie between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm Experimental evidence and practical implications of the proposed solution are given at the end of the paper For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool Fault coverage and test time are left unchanged by the proposed solution

/pdf/scan-cell-reordering-for-peak-power-reduction-during-scan-1ls7d90uhr.pdf

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time

Fast Bridging Fault Diagnosis using Logic Information

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated. Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then,it is shown that a bad result may be obtained if one of these criteria is not satisfied.

Christian Landrault

Papers

Slow write driver faults in 65nm SRAM technology: analysis and March test solution

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Fast Bridging Fault Diagnosis using Logic Information

On hardware generation of random single input change test sequences