A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.

A Gated Clock Scheme for Low Power Testing of Logic Cores

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Delay testing is a test procedure to verify the timing performance of manufactured digital circuits. A diagnosis process is often implemented after the detection of a fault in a circuit. Unfortunately, existing methodologies for locating delay defects on digital circuits have shown certain deficiencies. A new method for delay fault diagnosis, based on critical path tracing from a symbolic simulation, is presented. This method needs to consider only the fault-free circuit and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

Christian Landrault

Papers

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

A Gated Clock Scheme for Low Power Testing of Logic Cores

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

An alternative to fault simulation for delay-fault diagnosis

Delay fault diagnosis in sequential circuits based on path tracing