A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for this purpose two new models called hidden Markov model with patterns and independence model with patterns. Compared to existing methods, the proposed technique exhibits a very high fault coverage, including performance testing, at the expense of a low silicon area overhead.

Hidden Markov and independence models with patterns for sequential BIST

Test de Circuits et de Systèmes Intégrés

Power-Aware Scan Testing for Peak Power Reduction

In this paper, we present a method for diagnosing gate delay faults in synchronous sequential circuits. This method is an outgrowth of our previous work on delay fault diagnosis in combinational circuits, and is therefore based on a path tracing algorithm appropriate for sequential circuits. Input data for diagnosis are (1) the gate level description of the circuit, (2) the set of test sequences, and (3) the set of failing patterns and failing outputs provided by the tester. Output data are a set of potential fault locations. In order to correctly interpret the tester results, and avoid multiple fault effects and self-masking problems during diagnostic processing, each test sequence is considered under different combinations of slow and fast clock cycles (slow clock test methodology). Experimental results are given to show the feasibility, reliability and efficiency of the diagnosis method. >

/pdf/a-trace-based-method-for-delay-fault-diagnosis-in-4zqkf7ofxh.pdf

A trace-based method for delay fault diagnosis in synchronous sequential circuits

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.

Christian Landrault

Papers

Hidden Markov and independence models with patterns for sequential BIST

Test de Circuits et de Systèmes Intégrés

Power-Aware Scan Testing for Peak Power Reduction

A trace-based method for delay fault diagnosis in synchronous sequential circuits

A new test pattern generation method for delay fault testing