A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution

/pdf/minimizing-peak-power-consumption-during-scan-testing-test-4f13r8qlcv.pdf

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we use the classical triple modular redundancy (TMR) fault tolerant architecture as a case study. Firstly we analyze the conditions that make the use of TMR architectures interesting for yield improvement purpose. In the second part of the paper, we investigate the test requirements for the TMR architecture and we propose a solution for generating test patterns for this type of architecture. Finally, we propose a new manner to implement the TMR architecture that makes it very effective for yield improvement purpose. Experimental results are provided on ISCAS and ITC benchmark circuits to prove the efficiency of the proposed approach in terms of yield improvement with a low area overhead.

Using TMR Architectures for Yield Improvement

The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

A novel approach to delay-fault diagnosis

A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >

Delay-fault diagnosis by critical-path tracing

A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.

Christian Landrault

Papers

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

Using TMR Architectures for Yield Improvement

A novel approach to delay-fault diagnosis

Delay-fault diagnosis by critical-path tracing

High defect coverage with low-power test sequences in a BIST environment