A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

https://hal-lirmm.ccsd.cnrs.fr/docs/00/09/62/11/PDF/Landrault_ewdtw06.pdf

Framework for Logic Diagnosis

Autonomous Linear Finite State Machines with both complemented and uncomplemented register outputs (Mixed-Output ALFSMs) have been investigated for their use as Deterministic and Pseudo-random Test Vector Generators in a BIST scheme. We describe herein, a method for deriving the feedback connections of the Mixed-Output ALFSM given a deterministic sequence of n n-bit wide test vectors. We also show that the state graph structure is preserved thus enabling the generation of maaimum-length sequences if the characteristic polynomial of the connectivity matrix is primitive.

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors

An efficient solution for test pattern generation based on a switch-level description of complex CMOS circuits is presented To obtain gate-level speeds and to test realistic CMOS failures, this mixed-level approach recommends structural and functional grading during the preprocessing phase Conducting path analysis, relaxation algorithms, and truth-table analysis all contribute to functional grading Results show that the time required for these additional preprocessing steps is close to negligible compared to total CPU time During test pattern generation (TPG), fault injection can be performed at switch level with precise knowledge of CMOS technology, while the propagation and backtrace steps are applied to the circuit functional model Thus, classical TAG algorithms can be used Two learning techniques that mainly deal with the fault injection step and are compatible with most of the other published techniques are introduced Their use is optional in this mixed-level approach, but they can significantly speed up TPG >

Goovtant: an efficient mixed level ATPG to test realistic faults in complex CMOS circuits

An overview is presented of the different possibilities which allow the implementation of switch-level test pattern production for CMOS macrocells. A discussion is presented of fault modeling, fault list generation, circuit modeling and fault equivalence. Switch-level fault simulation is outlined along with switch-level ATPG (automatic test pattern generation). >

https://ieeexplore.ieee.org/iel2/335/6520/00257470.pdf

Christian Landrault

Papers

Framework for Logic Diagnosis

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors

Goovtant: an efficient mixed level ATPG to test realistic faults in complex CMOS circuits

Switch level test pattern production for CMOS ICs

Testability improvements using e-beam controllability: principle and design for electron-beam testability