A survey of maintenance policies of deteriorating systems

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test. In this article, we propose a global modeling allowing the definition of fault equivalence criteria in order to reduce the set of faults to be handled by the test pattern generation process for CMOS circuits. The proposed approach is based on a switch level description of the circuit. To perform fault equivalence on such descriptions, circuit modifications are introduced using subnetwork partitioning. The fault models taken into account are classical in CMOS technology, i.e., stuck-at, stuck-on, stuck-open, shorts and opens.

Fault modeling and fault equivalence in CMOS technology

A non-iterative gate resizing algorithm for high reduction in power consumption

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

https://www.computer.org/csdl/pds/api/csdl/proceedings/download-article/12OmNxVlTFS/pdf

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.

/pdf/efficient-3d-modelling-for-extraction-of-interconnect-28lclgblkg.pdf

Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

The embedded Flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. At first, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 µm eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the interest of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis on actual defects presented in [3] we are then able to enhance existing test solutions for eFlash testing.

Christian Landrault

Papers

Fault modeling and fault equivalence in CMOS technology

A non-iterative gate resizing algorithm for high reduction in power consumption

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash