Kuang-Hsin Chen

TL;DR: In this paper, the authors presented a leading edge 7nm CMOS platform technology for mobile SoC applications, which provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over 16nm FinFET technology.

TL;DR: The 5nm platform technology successfully passed qualification with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks, on schedule for high volume production in 1H 2020.

TL;DR: For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented and a fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V.

TL;DR: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, including providing semiconductor substrate having a pre-selected surface orientation and crystal direction, an insulator layer overlying the semiconductor substrategies, a first semiconductor active region extending through a thickness portion of the insulator layers having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconducting active region and a second

TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.