C
Cicero S. Vaucher
Researcher at NXP Semiconductors
Publications - 58
Citations - 1617
Cicero S. Vaucher is an academic researcher from NXP Semiconductors. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 18, co-authored 50 publications receiving 1530 citations. Previous affiliations of Cicero S. Vaucher include Philips.
Papers
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Journal ArticleDOI
A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology
TL;DR: In this article, a modular and power-scalable architecture for low-power programmable frequency dividers is presented, which consists of a 17-bit UHF divider, an 18-bit L-band divider and a 12-bit reference divider.
Journal ArticleDOI
A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems
Yikun Yu,Peter Baltus,A.J.M. de Graauw,E. van der Heijden,Cicero S. Vaucher,A.H.M. van Roermund +5 more
TL;DR: This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems.
Journal ArticleDOI
An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
TL;DR: In this article, an adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described, which combines contradictory requirements posed by different performance aspects such as settling time, phase noise, and spurious signals.
Book
Architectures for RF Frequency Synthesizers
Cicero S. Vaucher,Bram Nauta +1 more
TL;DR: The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects.
Book
Circuit Design for RF Transceivers
TL;DR: In this article, the authors present an approach to reduce the substrate bounce of a single-transistor LNA by reducing the number of transistors in the LNA and reducing the interference.