Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360° phase shift range in steps of approximately 22.5°, an average insertion gain of 12 dB at 61 GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360° phase shift range in 22.5° steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW.

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A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.
Written for:
Electrical and electronic engineers

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Architectures for RF Frequency Synthesizers

1. RF Design: Concepts and Technology 1.1 RF Specifications 1.1.1 Gain 1.1.2 Noise 1.1.3 Non-Linearity 1.1.4 Sensitivity 1.2 RF Device technology 1.2.1 Characterization and Modeling, Modeling, Cut-off Frequency, Maximum Oscillation Frequency, Input Limited Frequency, Output Limited Frequency, Maximum Available Bandwidth 1.2.2 Technology Choice, Double Poly Devices, Silicon-on-Anything, Comparison, SiGe Bipolar Technology, RF CMOS (updated for newer processes) 1.3 Passives 1.3.1 Resistors 1.3.2 Capacitors (updated for different layouts) 1.3.3 Planar Monolithic Inductors (updated as relation to newer processes) References (updated) 2. Antennas, Interface and substrate 2.1 Antennas 2.2 Bond wires 2.3 Transmission Lines 2.3.1 General Theory 2.3.2 Impedance Matching using Transmission Lines 2.3.3 Microstrip Lines and coplanar Lines 2.4 Bond Pads and ESD Devices 2.4.1 Bond Pads 2.4.2 ESD Devices, ggNMOST ESD Device, pn and np-diode ESD Device (updated for newer processes and detailed scaling effects) 2.5 Substrate 2.5.1 Substrate bounces 2.5.2 Design Techniques to Reduce the substrate bounce References (updated) 3. Low Noise Amplifiers 3.1 Specifications 3.2 Bipolar LNA designs 3.2.1 DCS applications in SOA, Design of the LNA, Measurements 3.2.2 Broadband LNA (new) 3.3 CMOS LNA Design 3.3.1 Single Transistor LNA, Design Steps, Simulation and Measurements 3.3.2 Classical LNA Design, The Design, Measurement Results 3.3.3 Broadband LNA (new) 3.4 Evaluation References (updated) 4. Mixers 4.1 Specification 4.2 Bipolar Mixer Design 4.3 CMOS mixers 4.3.1 Active CMOS mixer 4.3.2 Passive CMOS mixer, 1/f-Noise in mixer transistors, 1/f-Noise due to IF amplifier, 1/f-noise due to Switched-Capacitor Behavior 4.3.3 Concluding remarks References (Updated) 5. Case study Receiver front-ends (new) 5.1 Bluetooth (new) 5.2 IEEE 802.11a Standard (new) 6. RF Power Amplifier 6.1 Specification 6.1.1 Efficiency 6.1.2 Generic Amplifier Classes 6.1.3 Heating 6.1.4 Linearity 6.1.5 Ruggedness 6.2 Bipolar PA design 6.3 CMOS PA Design 6.4 Linearization Principles 6.4.1 Predistortion Technique 6.4.2 Phase-Correcting feedback 6.4.3 Envelope Elimination and Restoration (EER) 6.4.4 Cartesian Feedback 6.5 Case study: Bluetooth PA (new) References (updated) Note: Oscillator chapter: errors removed and updated throughout, sub-section headings probably quite similar but to be defined 7. Oscillators 7.1 Introduction 7.2 Specifications 7.3 LC oscillator 7.4 Ring oscillators 7.5 Phase noise modelling and simulation (new) 7.6 Typical oscillator performance (new) 7.7 Oscillator case studies (new), Wide range oscillators for mobile applications, Oscillators for ultra low-power wireless links, 10GHz CMOS VCO for WLAN, 10GHz QuBIC VCO for Satellite References (updated) 8. Frequency Synthesizers 8.1 Introduction 8.2 Integer-N PLL Architecture 8.3 Tuning System Specifications 8.3.1 Tuning Range 8.3.2

Cicero S. Vaucher

Papers

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Architectures for RF Frequency Synthesizers

Circuit Design for RF Transceivers