Light-Emitting Diodes. (Monographs in Electrical and Electronic Engineering.) By A. A. Bergh and P. J. Dean. Pp. viii+591. (Clarendon: Oxford; Oxford University: London, 1976.) £22.

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Light-emitting diodes

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

A new paradigm of predictive MOSFET and interconnect modeling is introduced. This approach is developed to specifically address SPICE compatible parameters for future technology generations. For a given technology node, designers can use default values or directly input L/sub eff/, T/sub ok/, V/sub t/, R/sub dsw/ and interconnect dimensions to instantly obtain a BSIM3v3 customized model for early stages of circuit design and research. Models for 0.18 /spl mu/m and 0.13 /spl mu/m technology nodes with L/sub eff/ down to 70 nm are currently available on the web. Comparisons with published data and 2D simulations are used to verify this predictive technology model.

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

https://web.iitd.ac.in/~mamidala/HTMLobj-1518/dopingless_TFET_TED_Final.pdf

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

High electrical conductivity and ampacity are usually mutually exclusive properties. Here, in a carbon nanotube–copper composite, Subramaniam et al. achieve a similar conductivity to copper, but with a hundred fold increase in current carrying capacity.

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One hundred fold increase in current carrying capacity in a carbon nanotube–copper composite

A simulation study on a new rectifier concept is presented. This device basically consists of two gates with different workfunctions on top of a thin intrinsic or lowly doped silicon body. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e., a charge plasma p-n diode is formed in which no doping is required. Simulation results reveal a good rectifying behavior for well-chosen gate workfunctions and device dimensions. This concept could be applied for other semiconductor devices and materials as well in which doping is an issue.

https://ris.utwente.nl/ws/files/6476584/hueting_edl.pdf

The Charge Plasma P-N Diode

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

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Fabrication and Characterization of the Charge-Plasma Diode

In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applied.

/pdf/low-frequency-noise-phenomena-in-switched-mosfets-jtp15rdx8v.pdf

Low-Frequency Noise Phenomena in Switched MOSFETs

A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 µm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs: primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors.

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An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

In this paper the texture, morphology, diffusion and electrical (de‐) activation of dopants in polycrystalline GexSi1-x and Si have been studied in detail. For gate doping B+,BF2+ and As+ were used and thermal budgets were chosen to be compatible with deep submicron CMOS processes. Diffusion of dopants is different for GeSi alloys, B diffuses significantly more slowly and As has a much faster diffusion in GeSi. For B doped samples both electrical activation and mobility are higher compared to poly‐Si. Also for the first time, BF2+ data of doped layers are presented, these show the same trend as the B doped samples but with an overall higher sheet resistance. For arsenic doping, activation and mobility are lower compared to poly‐Si, resulting in a higher sheet resistance. The dopant deactivation due to long low temperature steps after the final activation anneal is also found to be quite different. Boron‐doped GeSi samples show considerable reduced deactivation whereas arsenic shows a higher deactivation rate. The electrical properties are interpreted in terms of different grain size, quality and properties of the grain boundaries, defects, dopant clustering, and segregation, and the solid solubility of the dopants.

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Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-$Ge_xSi_1-x(x~0.3)$ as gate material for sub-0.25 µm complementary metal oxide semiconductor applications

Cora Salm

Papers

The Charge Plasma P-N Diode

Fabrication and Characterization of the Charge-Plasma Diode

Low-Frequency Noise Phenomena in Switched MOSFETs

An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-$Ge_xSi_1-x(x~0.3)$ as gate material for sub-0.25 µm complementary metal oxide semiconductor applications