Showing papers by "David Esseni published in 2014"
TL;DR: In this article, a two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor (Thin-TFET) is proposed and the tunneling current is calculated by using a formalism based on the Bardeen's transfer Hamiltonian, and including a semi-classical treatment of scattering and energy broadening effects.
Abstract: The single particle tunneling in a vertical stack consisting of monolayers of two-dimensional semiconductors is studied theoretically, and its application to a novel Two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor (Thin-TFET) is proposed and described. The tunneling current is calculated by using a formalism based on the Bardeen's transfer Hamiltonian, and including a semi-classical treatment of scattering and energy broadening effects. The misalignment between the two 2D materials is also studied and found to influence the magnitude of the tunneling current but have a modest impact on its gate voltage dependence. Our simulation results suggest that the Thin-TFETs can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. The Thin-TFET is thus very promising as a low voltage, low energy solid state electronic switch.
109 citations
TL;DR: The device-circuit interaction in n- and p-type TFETs is explored, and a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow VDD is proposed, as required inUltralow voltage systems.
Abstract: This paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a V
DD
below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device-circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V
DD
, as required in ultralow voltage systems. Then, we systematically compare the I
OFF
, I
ON
, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V
DD
. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.
56 citations
TL;DR: A simple approach to describe electrolytes in TCAD simulators for the modeling of nano-biosensors is presented, exploiting the similarity between the transport equations for electrons and holes in semiconductors and the ones for charged ions in a solution.
Abstract: We present a simple approach to describe electrolytes in TCAD simulators for the modeling of nano-biosensors. The method exploits the similarity between the transport equations for electrons and holes in semiconductors and the ones for charged ions in a solution. We describe a few workarounds to improve the model accuracy in spite of the limitations of commercial TCAD. Applications to the simulations of silicon nanowire and nano-electrode biosensors are reported as relevant examples.
49 citations
TL;DR: In this article, a comparative simulation study of ultrathin-body InAs, InAs and strained Si MOSFETs was performed using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model.
Abstract: Thanks to the high electron velocities, III–V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ , and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III–V and Si nanoscale MOSFETs with a given gate length $({L}_{{G}})$ may have a quite different effective channel length $({L}_{{\rm eff}})$ ; 2) the difference in ${L}_{{\rm eff}}$ provides a useful insight to interpret the performance comparison of III–V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III–V MOSFETs.
36 citations
07 Apr 2014
TL;DR: In this paper, a simple analytic model based on the Kane-Sze formula is proposed to describe the currentvoltage characteristics of tunnel field effect transistors (TFETs), which captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic.
Abstract: A simple analytic model based on the Kane-Sze formula is proposed to describe the current-voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.
33 citations
TL;DR: In this article, a new model for the surface roughness (SR) limited mobility in MOS transistors is presented, which is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement Δ of the interface position and the SR scattering matrix elements.
Abstract: This paper presents a new model for the surface roughness (SR) limited mobility in MOS transistors. The model is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement Δ of the interface position and the SR scattering matrix elements, which is found to significantly influence the r.m.s value (Δrms) of the interface roughness that is necessary to reproduce SR-limited mobility measurements. In particular, comparison with experimental mobility for bulk Si MOSFETs shows that with the new SR scattering model a good agreement with measured mobility can be obtained with Δrms values of about 0.2 nm, which is in good agreement with several AFM and TEM measurements. For thin body III–V MOSFETs, the proposed model predicts a weaker mobility degradation at small well thicknesses (Tw), compared to the Tw6 behavior observed in Si extremely thin body devices.
28 citations
TL;DR: In this article, the authors examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain, and developed a model to calculate the currentvoltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base collector dielectrics that distort the potential profile and limit the upper value of \(f_T''.
Abstract: We examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain. To this purpose, we developed a model to calculate the current-voltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base-collector dielectrics that distort the potential profile and limit the upper value of \(f_T\) . Model predictions are compared with available experiments. We show that, in spite of space charge high current effects, optimized GBT designs still hold the promise to achieve intrinsic cutoff frequency in the terahertz region, provided that an appropriate set of dielectric and emitter materials is chosen.
28 citations
TL;DR: This investigation permits to understand the potential of TFETs and their advantages over traditional devices within a unitary framework that is based on fair design and comparison from device to circuit level, as well as to develop clear design perspectives in the context of ULV/ULP VLSI digital circuits.
Abstract: In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of appropriate reference circuits. Critical issues arising at ultra-low voltages are analyzed, including static robustness of TFET logic gates, performance degradation, and sensitivity to process variations. Guidelines to design ultra-low energy standard cell libraries are derived. The minimum energy point is analyzed in a wide range of conditions, and guidelines for microarchitectural optimization for ultra-low energy are introduced. Voltage scalability of static RAM memories is also analyzed as main limitation to aggressive voltage scaling of very large scale integration (VLSI) systems, and improved precharge schemes are introduced to reduce leakage. The impact of variations of the main device parameters on VLSI digital circuits is investigated to identify the most critical variations that need to be controlled at process level. This investigation permits to understand the potential of TFETs and their advantages over traditional devices within a unitary framework that is based on fair design and comparison from device to circuit level, as well as to develop clear design perspectives in the context of ULV/ULP VLSI digital circuits.
28 citations
TL;DR: In this article, a grading of the molar fraction in the source region of III-V hetero-junction tunnel-FETs is proposed to improve the on-current without degrading the sub-threshold swing.
Abstract: We propose to employ a grading of the molar fraction in the source region of III-V hetero-junction tunnel-FETs as a means to improve the on-current without degrading the subthreshold swing. Our full quantum simulations show that the molar-fraction grading increases the on-current by enlarging the hole wave function penetration from the source to the channel region. We also compare the performance of graded AlGaSb/InAs tunnel FETs and InAs MOSFETs and show that at VDS=0.3 V, the tunnel device can outperform the MOSFET in terms of both on-current and subthreshold slope.
26 citations
TL;DR: In this article, the analog/RF intrinsic performance of graphene FETs through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, was assessed.
Abstract: We assess the analog/RF intrinsic performance of graphene FETs (GFETs) through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, validated by comparison with full quantum results over a wide range of bias voltages. We found that scaling is expected to improve the fT, and that scattering plays a role in reducing both the fT and the transconductance also in sub-100-nm GFETs. Moreover, we observed a strong degradation of the device performance due to the series resistances and source/drain to channel underlaps.
18 citations
01 Dec 2014
TL;DR: In this paper, the authors employ a state-of-the-art Multi-Subband Monte Carlo simulator to investigate the performance of III-V n-MOSFETs with L G = 11.7nm.
Abstract: In this work we employ a state-of-the-art Multi-Subband Monte Carlo simulator to investigate the performance of III–V n-MOSFETs with L G = 11.7nm. We analyze GaSb versus InGaAs strained and unstrained channel materials and the implications of Fermi level pinning on electrostatic and transport. We found that InGaAs MOSFETs can outperform strained silicon for low V DD applications. Advantages related to strained InGaAs are limited and mainly due to reduced Fermi Level Pinning.
06 Nov 2014
TL;DR: The results suggest that ambipolarity needs to be solved through device engineering and/or fabrication process improvements, while issues related to uni-directionality may be mitigated with a proper circuit design.
Abstract: Tunnel-FETs are studied in a mixed device/circuit simulation environment. Model parameters calibrated on experimental DC as well as pulsed characterizations are then used for 6T SRAM cells investigation. Issues concerning fabricated devices, as the ambipolarity and the uni-directionality, are addressed at both device and circuit levels. Our results suggest that ambipolarity needs to be solved through device engineering and/or fabrication process improvements, while issues related to uni-directionality may be mitigated with a proper circuit design. Keywords—TCAD; Tunnel-FET; Ambipolarity; SRAM.
TL;DR: In this article, the authors presented the solution of the Schrodinger-Poisson coupled problem for nanoscale electron devices obtained by means of the Discrete Geometric Approach (DGA).
Abstract: This paper presents the solution of the Schrodinger---Poisson coupled problem for nanoscale electron devices obtained by means of the Discrete Geometric Approach (DGA) The paper illustrates a self-contained description of the DGA method for a Schrodinger---Poisson problem, discusses its implementation and compares the results of the DGA with respect to the ones obtained by the well established Pseudo-spectral (PS) method for two technologically relevant benchmark devices (ie a nanowire and a FinFET) Finally, the paper examines the merits of the DGA approach with respect to the Finite Differences (FD) and Finite Elements (FE), that are the most frequently used methods in the electron device community
22 Jun 2014
TL;DR: In this paper, the authors used TCAD mixed device-circuit simulations of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si-TFET designed in [3] (Fig. 1) for low voltage regime (below 0.2V) and showed that ambipolarity is limited in these devices.
Abstract: Tunnel-FET is one of the most promising candidates to replace CMOS in low-power (LP) applications [1], featuring a sub-threshold slope (SS) below the 60mV/dec limit of MOSFET. However, the intrinsic asymmetry of TFETs, makes them good transistors only for a current flowing from drain to source and prevents their use as access transistors (AT) in the 6T SRAM cell. In this paper, we use TCAD mixed device-circuit simulations [2] of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si TFET designed in [3] (Fig. 1) for V
DD
as low as 0.2V. The gate metal work-functions were set to match the off-current for LP applications (10pA/μm). For comparison purposes, both N- and P-MOS were also designed with the same double-gate SOI structure. The I
D
-V
GS
curves of the TFETs (Fig.2) show that the sub-60mV/decade region is confined to ultra low voltage regime (below 0.25 V) and that ambipolarity is very limited in these devices. I
D
(V
DS
) in Fig.3 show the lower output conductance of the TFETs w.r.t. to MOS.
08 Jun 2014
TL;DR: In this paper, the transport properties of 2D crystal semiconductors from two angles are investigated, and scattering mechanisms that limit the electron mobility are identified, and means to improve them vastly over currently reported values are presented.
Abstract: In this work, we investigate the transport properties of 2D crystal semiconductors from two angles. For drift transport in traditional FETs, scattering mechanisms that limit the electron mobility are identified, and means to improve them vastly over currently reported values are presented. For low-power electronics, tunneling transport currents within monolayer p-n junctions, and interlayer tunneling currents between adjacent 2D semiconductor layers is discussed for TFETs.
22 Jun 2014
TL;DR: In this article, the effect of the lateral transport on the on-current area density and the sub-threshold swing of the thin-TFET was studied in the top and bottom 2D layers of a two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor.
Abstract: The single particle model has been developed for the tunneling between two monolayer two-dimensional (2D) semiconductors [1]. Based on this model, a novel Two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor (Thin-TFET) (see Fig.1a) is proposed to achieve very steep subthreshold swing [1]. However, the initial study ignored the lateral transport in the top and bottom 2D layers. In this work, we study the effect of the lateral transport on the on-current area density and the sub-threshold swing (SS) of the Thin-TFET.
22 Jun 2014
TL;DR: A device-circuit co-design of n- and p-type Tunnel FETs leading to a good tradeoff between current leakage, effective capacitance and transistor imbalance at ultra-low VDD is illustrated.
Abstract: This paper presents a comparative study between Tunnel-FETs (TFETs) and SOI MOSFETs for ultra-low power digital circuits targeting ultra-low voltages (below 500mV). We illustrateg a device-circuit co-design of n- and p-type Tunnel FETs leading to a good tradeoff between current leakage, effective capacitance and transistor imbalance at ultra-low V DD . TFETs and MOSFETs at 30 nm gate length are compared in terms of DC robustness, effect of transistor stacking, performance and potential for minimum-energy operation under aggressive voltage scaling.
07 Apr 2014
TL;DR: In this article, the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schrodinger-Poisson and Multi-subband Monte Carlo simulations is investigated.
Abstract: We investigate the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schro¨dinger-Poisson and Multi-subband Monte Carlo simulations. Traps in the conduction band are found to be the main responsible of the Fermi level pinning observed in the experiments. These traps impact the mobility measurements as well as the current drive of short channel devices.
01 Sep 2014
TL;DR: From the perspective of technology scaling, the analysis shows that TFETs can significantly relax the physical-level constraints on gate pitch, thereby mitigating the printability issues in 32-nm technologies and beyond.
Abstract: In this paper, the potential of Tunnel FETs (TFETs) for ultra-low power operation is investigated in the context of digital circuits operating below 500 mV. A comparative analysis of TFETs and SOI CMOS in 32 nm technology is performed through device- and circuit-level simulations, based on a unitary simulation framework where all devices are fairly designed for the same (low) voltage range and the same device-level targets.The performance is evaluated through figures of merit at device and circuit level, quantifying the impact of each device parameter on the performance. The analysis considers both the nominal corner and the impact of the variations of various device parameters, which is evaluated through sensitivity analysis. The results permit to identify the most critical TFET parameters subject to variations that require finer control at process level, to keep circuit-level variations within reasonable bounds. From the perspective of technology scaling, the analysis shows that TFETs can significantly relax the physical-level constraints on gate pitch, thereby mitigating the printability issues in 32-nm technologies and beyond.
20 Nov 2014
TL;DR: In this paper, a comparative analysis of TFETs, SOI and bulk CMOS in 32 nm technology is performed through device- (TCAD) and circuit-level (VerilogA) simulations.
Abstract: In this paper, the advantages and the challenges posed by Tunnel FETs (TFETs) are studied in the context of ultra-low voltage SRAM bitcells operating below 500 mV. A comparative analysis of TFETs, SOI and bulk CMOS in 32 nm technology is performed through device- (TCAD) and circuit-level (VerilogA) simulations. Sensitivity to the key device parameters is analyzed to quantitatively evaluate the impact of the corresponding variations. Interestingly, our analysis shows that TFETs are less sensitive than SOI/bulk to device parameters that are affected by the gate pitch. Hence, TFETs can help mitigate the printability issues in 32-nm technologies and beyond.