Showing papers in "Solid-state Electronics in 2014"

Reconfigurable nanowire electronics – A review

Abstract: Reconfigurable nanowire transistors merge the electrical properties of unipolar n- and p-type FETs into a single type of device with identic technology, geometry and composition. These four-terminal nanowire transistors employ an electric signal to dynamically program unipolar n- or p-type behavior. More than reducing the technological complexity, they open up the possibility of dynamically programming the functions of circuits at the device level, i.e. enabling a fine-grain reconfiguration of complex functions. We will review different reconfigurable concepts, analyze the transport properties and finally assess their maturity for building circuits.

Low temperature acetone detection by p-type nano-titania thin film: Equivalent circuit model and sensing mechanism

Abstract: Undoped nanocrystalline anatase p-type TiO2 thin film was deposited by sol–gel method on thermally oxidized p-Si (2–5 Ω cm, 〈1 0 0〉) substrates. The thin film was characterized by X-ray Diffraction (XRD) and Field Emission Scanning Electron Microscopy (FESEM) to confirm the formation of nanocrystalline anatase titania and to determine the crystallite size (∼7 nm). The resistive sensor structure was fabricated employing two lateral Pd electrodes on top of the TiO2 sensing layer. The developed sensor was tested in the temperature range of 50–200 °C for the detection of low ppm acetone (0.5–50 ppm). The maximum response of ∼115% was obtained at 150 °C with response/recovery time of 14 s/22 s at 50 ppm acetone (in air). Moreover, the sensors were capable of detecting acetone as low as 0.5 ppm with acceptable response magnitude. As titania acetone sensors are mostly n-TiO2 based, the acetone sensing mechanism for p-TiO2 is yet to be established authentically. To address the issue, an equivalent circuit model, based on the corresponding band diagram of nanocrystalline p-TiO2 with Pd electrode, was developed to describe the electron transfer mechanism through grain, grain boundary and Pd electrode under the influence of acetone vapor.

Models for the use of commercial TCAD in the analysis of silicon-based integrated biosensors

Abstract: We present a simple approach to describe electrolytes in TCAD simulators for the modeling of nano-biosensors. The method exploits the similarity between the transport equations for electrons and holes in semiconductors and the ones for charged ions in a solution. We describe a few workarounds to improve the model accuracy in spite of the limitations of commercial TCAD. Applications to the simulations of silicon nanowire and nano-electrode biosensors are reported as relevant examples.

Chemical vapor sensing of two-dimensional MoS2 field effect transistor devices

Abstract: MoS 2 , in single to few-layer format, is of interest because of its potential for advanced transistor and sensor applications. Its sizable bandgap enables single layer transistors with large on/off current ratios, and the large surface-to-volume ratio provides sensitive transduction of surface physisorption to the channel conductivity. Here, we discuss aspects of transistor device fabrication and of chemical vapor sensing experiments. We expose MoS 2 chemical sensors to a variety of analytes, find the largest response to triethylamine, a nerve gas by-product, and explain our results based on a donor–acceptor model. We show that our MoS 2 sensors provide comparable sensitivity and much higher selectivity than other low-dimensional sensors such as carbon nanotube and graphene chemical sensors. We present results for back-gated sensing and light sensitivity for our monolayer MoS 2 sensors, and compare the results with multilayer MoS 2 sensors.

Device design assessment of 4H–SiC n-IGBT – A simulation study

Abstract: A theoretical design assessment is presented using two dimensional numerical computer aided design (TCAD) tool for 15–20 kV 4H–SiC IGBTs. Physical parameters of the layer structures such as drift layer thickness, doping in the drift layer, JFET region width and interface charges underneath the gate region are varied to predict the device performance. Performance is further assessed at different temperatures and with different carrier lifetime in the drift layer. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. Simulations show that a minority carrier lifetime in the drift layer of 1.0–1.6 μs produces a close match with the experimental device. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier lifetime), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier lifetime is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 K) due to decrease in the carrier mobility. A significant increase in the forward voltage drop is observed with the presence of interface trap charges. Increasing JFET region width slightly decreases the forward on-state voltage. A drift layer of at least 175 μm thick with a doping concentration of

Z2-FET: A promising FDSOI device for ESD protection

Abstract: In this work, the use of the Z 2 -FET (Zero subthreshold swing and Zero impact ionization FET) for Electro-Static Discharge (ESD) protections is demonstrated. The device, fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator technology, features an extremely sharp off-on switch and an adjustable triggering voltage ( V t 1 ). The principle of operation, relying on the modulation of electron and hole injection barriers, is reviewed. The impact of process modules and design parameters on electrical characteristics is analyzed with TCAD simulations, showing that very low leakage current ( I leak ) and triggering capability adapted to local protection schemes are achievable. Experimental results validate the possible use of this device as an ESD protection in the 28 nm FDSOI technology.

Proximity gettering of slow diffuser contaminants in CMOS image sensors

Abstract: In complementary metal–oxide-semiconductor (CMOS) imager sensors, metallic contamination is a critical issue because it induces dark current and increases yield loss. Therefore, the challenge is to identify and eliminate progressively lower doses of metallic contamination. In recent years, Mo and W have received much attention because of their adverse effect on image sensor quality. This paper presents data from the testing of proximity gettering layers obtained by C or Si implantation, for what concerns their efficiency in Mo and W gettering. Deep-level transient spectroscopy (DLTS) was used to measure the impurity concentration in solid solution to evaluate gettering efficiency. Carbon implantation was found to be effective in capturing impurities, whereas Si implantation was not effective. Extended defects did not play a relevant role in gettering impurities, while gettering was found to be most effective in high impurity concentrations.

Characterization of deep electron traps in 4H-SiC Junction Barrier Schottky rectifiers

Abstract: Conventional deep level transient spectroscopy (DLTS) technique was used to study deep electron traps in 4H-SiC Junction Barrier Schottky (JBS) rectifiers. 4H-SiC epitaxial layers, doped with nitrogen and grown on standard n+−4H-SiC substrates were exposed to low-dose aluminum ion implantation process under the Schottky contact in order to form both JBS grid and junction termination extension (JTE), and assure good rectifying properties of the diodes. Several deep electron traps were revealed and attributed to impurities or intrinsic defects in 4H-SiC epitaxial layers, on the basis of comparison of their electrical parameters (i.e. activation energies, apparent capture cross sections and concentrations) with previously published results.

Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit

Abstract: This work details the harmful effect of parasitic resistances and capacitances on RF figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) FD SOI n-MOSFETs. It is demonstrated that intrinsically, UTBB device can reach very high cut-off frequency (fT) provided the reduction of parasitic elements. In addition, based on device simulation, we demonstrate that with appropriate configuration, Asymmetric Double Gate (ADG) regime provides a slight improvement of RF figures-of-merit.

Incremental resistance programming of programmable metallization cells for use as electronic synapses

Abstract: In this work, we investigate the resistance switching behavior of Ag–Ge–Se based resistive memory (ReRAM) devices, otherwise known as programmable metallization cells (PMC). The devices studied are switched between high and low resistive states under externally applied electrical bias. The presence of multiple resistive states observed under both dc and pulse voltage application makes these devices promising candidates for use as electronic synapses in neuromorphic hardware implementations. Finally, the effect of varying pulse voltage magnitude and width on the change in resistance is observed through measurement.

SOI dual-gate ISFET with variable oxide capacitance and channel thickness

Abstract: A dual-gate (DG) ion sensitive field effect transistor (ISFET) using capacitance coupling effect has recently been proposed to overcome the Nernst limitation as 59 mV/pH. In this study, we focus on the analysis of sensing characteristics by various oxide capacitances and channel thickness using intensive measurement on conventional fully depleted (FD) silicon-on-insulator (SOI) based DG ISFET. The enlarged oxide capacitance and reductive channel thickness enhance the capacitive coupling effect and increase sensitivity of DG ISFET. And also, the thin channel thickness reduced the leakage current in the DG operation. These will be very promising techniques for high performance biosensor application.

Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Abstract: Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

Characteristics of GaN and AlGaN/GaN FinFETs

Abstract: AlGaN/GaN FinFETs, with high quality atomic layer deposited (ALD) Al2O3 gate dielectric, have been fabricated. The devices have a two-dimensional electron gas (2DEG) channel formed at AlGaN/GaN heterointerface and two sidewall GaN MOS channels. Two distinct transconductance peaks can be observed, one for the 2DEG channel and the other for the sidewall GaN MOS channels. On the other hand, we present heterojunction-free GaN FinFETs with junctionless configuration. The current flows through the volume of the heavily doped GaN fin rather than at the surface channel, which leads to superior off-state performance and less drain-induced virtual substrate biasing (DIVSB) effect.

ON-state characteristics of proton irradiated 4H–SiC Schottky diode: The calibration of model parameters for device simulation

Abstract: 4H silicon carbide Schottky diodes were irradiated by 550 keV protons with the aim to place the ion range into the low-doped n -type epitaxial layer. The diodes were characterized using DLTS, C – V profiling and forward I – V curves. Calibration procedure of model parameters for device simulation has been carried out. It is based on modeling the doping compensation of the n -type epitaxial layer caused by the deep acceptor levels resulting from radiation damage. It is shown that the agreement of simulated and measured forward I – V curves of proton irradiated diodes can be achieved, if the profiles of deep levels are calibrated with respect to irradiation dose, the degradation of electron mobility due to charged deep levels is accounted of and the Schottky barrier height is properly adjusted. The proposed methodology introduces a starting point for exact calibration of ion irradiated SiC unipolar devices.

Modeling of sheet carrier density and microwave frequency characteristics in Spacer based AlGaN/AlN/GaN HEMT devices

Abstract: In this paper, we present a physics-based model for two-dimensional electron gas (2DEG) sheet carrier density n s and various microwave characteristics such as transconductance, cut-off frequency ( f t ) of the proposed Spacer layer based Al x Ga 1− x N/AlN/GaN High Electron Mobility Transistors (HEMTs) is modeled by considering the quasi-triangular quantum well. To obtain charge density n s , the variation of Fermi level with supply voltage and the formation of various energy sub-bands E 0 , E 1 are considered. The obtained results are simple and easy to analyze the sheet carrier density, DC model and microwave frequency performance analysis for nanoscale Spacer layer based Al x Ga 1− x N/AlN/GaN HEMT power devices. The Spacer layer based AlGaN/AlN/GaN heterostructure HEMTs shows excellent promise as one of the candidates to substitute present AlGaN/GaN HEMTs for future high speed and high power applications. Derived model results for drain current, transconductance, current-gain cutoff frequency for different short and long gate length device are calibrated and verified with experimental data over a full range for gate and drain applied voltages and is useful for nanoscale and microwave analysis for circuit design.

Process dependency on threshold voltage of GaN MOSFET on AlGaN/GaN heterostructure

Abstract: GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) with recessed gate on AlGaN/GaN heterostructure are reported in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. Negative threshold voltages were commonly observed in all devices. To investigate the reasons of the negative threshold voltages, different oxide thickness, etching gas and bias power of inductively-coupled plasma (ICP) system were utilized in the fabrication process of the GaN MOSFETs. It is found that positive charges of around 1 × 10 12 q/cm 2 exist near the interface at the just threshold condition in both silane- and tetraethylorthosilicate (TEOS)-based devices. It is also found that the threshold voltages do not obviously change with the different etching gas (SiCl 4 , BCl 3 and two-step etching of SiCl 4 /Cl 2 ) at the same ICP bias power level (20–25 W) and will become deeper when higher bias power is used in the dry recess process which may be related to the much serious ion bombardment damage. Furthermore, X-ray photoelectron spectroscopy (XPS) experiments were done to investigate the surface conditions. It is found that N 1s peaks become lower with higher bias power of the dry etching process. Also, silicon contamination was found and could be removed by HNO 3 /HF solution. It indicates that the nitrogen vacancies are mainly responsible for the negative threshold voltages rather than the silicon contamination. It demonstrates that optimization of the ICP recess conditions and improvement of the surface condition are still necessary to realize enhancement-mode GaN MOSFETs on AlGaN/GaN heterostructure.

Threshold voltage extraction in Tunnel FETs

Abstract: This article proposes two possible extrapolation-type methods to extract the threshold voltage of Tunnel Field Effect Transistors (TFETs). The first one, which we call the “ CTR method,” makes use of the drain Current-to-Transconductance Ratio function. As this method requires differentiating the drain current with respect to the gate voltage, it is blurred by the amplified effect of measurement noise when applied to real device transfer characteristics. To avoid this effect, a second method is also proposed that uses integration of the drain current with respect to gate voltage instead of differentiation. This second method, which was named “ H 1 method” when it was originally applied to non-crystalline inversion mode MOSFETs, produces comparable results to those obtained from the CTR method, but it has the advantage of inherently reducing the effect of measurement noise by virtue of the low-pass filtering capacity of integration. Both methods are based on defining threshold voltage as the gate voltage axis intercept of the linearly extrapolated strong conduction behavior of either CRT or H 1 functions. This is made possible by approximating the drain current in the strong conduction region of the TFET’s transfer characteristics by a monomial function of the gate voltage. Both methods are illustrated and compared by applying them to measured transfer characteristics of experimental Fin-type TFETs.

Analysis of temperature dependent hysteresis in MoS2 field effect transistors for high frequency applications

Abstract: Thermal and hysteresis effects are studied for the first time in Al 2 O 3 top-gated, CVD grown monolayer MoS 2 field effect transistors (FETs). Stressing with an applied bias reversed the hysteresis rotation in the high temperature I ds – V gs transfer characteristics and this behavior, indicative of a multilevel trap model, was explained by charge carriers interacting with traps possibly at the MoS 2 /dielectric interface and within the CVD grown MoS 2 . High temperature FET characteristics measured up to 125 °C demonstrated pinch-off degradation and the influence of trapping/detrapping rates in both the top and bottom gate dielectric. This indicates the importance of maintaining oxide and interface quality for good FET performance.

Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics

Abstract: In this paper, UTBOX nMOSFETs with different gate dielectrics have been studied based on their low-frequency noise (LFN) performance. Since LFN measurements have been successfully used as a characterization tool for determining the quality of the films, here, we have investigated the dielectric films used in state-of-the-art UTBOX devices in order to evaluate their performance and to identify the type of traps possibly introduced during the device processing. High-k gate dielectric devices have shown predominantly 1/ f noise with a two-order of magnitude higher value than the conventional SiO 2 ones which, consequently, results in higher density of traps in those devices. The carrier number fluctuations dominate the 1/ f noise for both front and back interfaces. Due to the thin silicon film thickness there is a strong electrostatic coupling between front and back interfaces that interferes in the noise results as well as in transistor parameters. A contribution of the back interface noise source of about 14% on the measured noise in the front channel conduction was found, while the contribution of the front interface noise source is about 22% on the measured noise in the back channel conduction. The generation–recombination (GR) noise performed at different temperatures has enabled the identification of 6 types of traps and 2 unknown ones, being originated from the dry-etching or implantation damage.

A defect-based compact modeling approach for the reliability of CMOS devices and integrated circuits

Abstract: Reliability simulations are critical for lifetime prediction and verification of long-term performance of integrated circuits designed in advanced CMOS technologies. The existing techniques for reliability simulation model aging effects using threshold voltage ( V th ) shifts that do not reflect the bias-dependence of stress-induced defects. In this work we present a defect-based modeling approach that captures the dynamic effects of both oxide-trapped charge and interface traps through calculations of surface potential. Such defects are attributed to aging effects and to ionizing–radiation damage in advanced CMOS technologies. The approach provides a connection between physics-based reliability models and integrated circuit simulation. The model is implemented as a Verilog-A sub-circuit module and is compatible with standard EDA tools and MOSFET compact models. The model formulation is verified using two-dimensional TCAD simulations. Demonstrations with digital integrated circuit simulations in SPICE and comparisons with calculations using V th -based models are also presented.

Trans-capacitance modeling in junctionless gate-all-around nanowire FETs

Abstract: In this brief, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET) As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme recently pointed out between JL NW FET and its double gate counterpart for which such a model has been proposed This approach is validated by 3D Technology Computer Aided Design simulations and bridges the gap between the nanowire junctionless device and its application in circuits

ZnO based UV detectors with Surface Plasmon Polariton enhancement on responsivity

Abstract: We have fabricated Surface Plasmon Polariton (SPP) enhanced ZnO based Metal–Semiconductor–Metal (MSM) photoconductive UV detectors with the introduction of Ag nanoparticles. The absorption spectra show two SPP resonance peaks located at 321 nm and 389 nm, respectively. Annealing in Ar atmosphere leads to a red-shift for the long wavelength peak due to an increase of the average size of Ag particles and congregation of them. The experiment data agrees well with the computing result based on Mie theory. And the responsivity enhancement is demonstrated by the fact that the peak responsivity (at 350 nm) increases by more than 100 times, from 472 mA W−1 to 51.3 A W−1.

Resistive switching of Cu/SiC/Au memory devices with a high ON/OFF ratio

Abstract: Resistive memories (RMs) using amorphous SiC (a-SiC) as the solid electrolyte material have been developed with a Cu/a-SiC/Au stack configuration. Excellent non-volatile bipolar switching characteristics have been observed. An extremely high ON/OFF current ratio in the order of 109 has been observed corresponding to distinctive low (LRS) and high (HRS) resistance states, which is potentially beneficial for future RM applications with reliable state detection and simple periphery circuits. The deposited a-SiC has been extensively characterised for its micro/nanostructures, chemical composition as well as electrical properties. The switching mechanism is investigated through detailed analysis of corresponding I–V curves. The results imply a filamentary conduction mechanism at LRS and Schottky emission mechanism at HRS, especially in the subsequent switching cycles. The contrasting conducting material properties and mechanisms at LRS and HRS contribute to the high ON/OFF ratio. Overall, Cu/a-SiC based RMs demonstrate a number of high performance potentials.

A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects

Abstract: In this paper, a threshold voltage model of short-channel recessed-source/drain (Re-S/D) ultra-thin body (UTB) SOI MOSFETs has been presented considering the substrate induced surface potential (SISP) to improve the model accuracy over wide ranges of device parameters and substrate bias. The potential distribution of the front and the back surfaces of the Si-body have been derived using the evanescent mode analysis method in which the channel potential is broken into one-dimensional long-channel potential and two-dimensional short-channel potential. A one-dimensional Poisson’s equation has also been solved in the substrate region to account the effect of substrate induced surface potential (SISP) at substrate/buried-oxide interface. The minimum front- and back-surface potentials of silicon body have been used to obtain front and back channel threshold voltages, respectively. However, the smaller one between front and back channel threshold voltages is considered to be the threshold voltage of the device. The accuracy of the present model has been extended up to 10 nm channel length by incorporating the quantum effects induced correction term. The model results are verified with simulation results obtained using ATLAS™ from Silvaco.

Performance improvement of oxide thin-film transistors with a two-step-annealing method

Abstract: In this paper, a thin-film transistor (TFT) with indium zinc oxide (IZO) channel layer was fabricated using a two-step-annealing method in which the IZO film experienced annealing steps before the etch-stopper-layer formation and after the whole device completion. The device showed better uniformity and better stability under positive bias stress, negative bias illumination stress, and temperature stress, compared to those with only one post annealing step. The calculated falling rate of the Fermi lever of the IZO channel for the two-step annealing device was as high as 0.593 eV/V, compared to 0.213 eV/V for the only-post-annealing-step one. And the corresponding density of subgap state was 4.4 × 1015 and 1.6 × 1016 eV−1 cm−3 for the device with two annealing steps and with only one post annealing step, respectively.

Compact core model for Symmetric Double-Gate Junctionless Transistors

Abstract: A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation.

Cryogenic noise performance of InGAAs/InAlAs HEMTs grown on InP and GaAs substrate

Abstract: We present a comparative study of InGaAs/InAlAs high electron mobility transistors (HEMTs), intended for cryogenic ultra-low noise amplifiers (LNAs) and fabricated on different substrate and buffer technologies. The first was pseudomorphically grown on InP (InP pHEMT) while the second was grown on a linearly graded metamorphic InAlAs buffer on top of a GaAs substrate (GaAs mHEMT). Both HEMTs had identical active epitaxial regions. When integrated in a 4–8 GHz 3-stage LNA at 300 K, the measured average noise temperature was 45 K for the InP pHEMT and 49 K (9% higher) for the GaAs mHEMT. When cooled down to 10 K, the InP pHEMT LNA was improved to 1.7 K whereas the GaAs mHEMT LNA was only reduced to 4 K (135% higher). The observed superior cryogenic noise performance of the HEMTs grown on InP is believed to be due to a higher carrier confinement within the channel. Microscopy analysis suggested this was related to defects from the metamorphic buffer of the GaAs mHEMT.

Reliability of ultra-thin buried oxides for multi-VT FDSOI technology

Abstract: This paper investigates the intrinsic reliability of ultra-thin buried oxides (UTBOX) integrated in the last generation of FDSOI wafers obtained by the Smart Cut™ technology. In term of breakdown reliability, these state-of-the-art UTBOX oxides exhibit comparable performances with thermally-grown SiO 2 references. In “the worst case condition”, the voltage for a 10 years lifetime of 25 nm thick BOX, is estimated to 14 V, which largely exceeds the maximum operating conditions for back-bias [+3 V, –3 V] in advanced FDSOI integrated circuits. This makes UTBOX family of engineered substrates fully compatible and suitable for multi- V T applications.

Compact modeling of STT-MTJ devices

Abstract: STT-MTJ is a promising device for future high-density and low-power integrated systems. To enable design exploration of STT-MTJ, this paper presents a fully compact model for efficient SPICE simulation. Derived from the fundamental LLG equation, the new model consists of RC elements that are compact equations of device geometry and material properties. They support transient SPICE simulations, providing necessary details beyond the macromodel and enable resilient memory design. The accuracy of the model is validated with numerical results and published data. Scaling analysis shows the sensitivity of STT-MTJ to its geometry. We also did variability analysis with Monte Carlo simulation of the basic 1T1MTJ memory cell to study the bit error rate performance for different transistor size and programming current profile. We show that there is a tradeoff between programming energy and cell area for the same bit error rate constraint. Finally we derive the cell size that achieves minimum energy consumption for a given bit error rate constraint (primary) and latency or area constraint (secondary).

A study on HfO2 RRAM in HRS based on I–V and RTN analysis

Abstract: This paper presents a statistical characterization of random telegraph noise (RTN) in hafnium-oxide-based resistive random access memories (RRAMs) in high resistive state (HRS). Complex RTN signals are analyzed exploiting a Factorial Hidden Markov Model (FHMM) approach, which allows to derive the statistical properties of the RTN signals, directly related to the physical properties of the traps responsible for the multi-level RTN measured in these devices. Noise characteristics in different reset conditions are explored through consecutive switching cycles. Noise spectral analysis is also performed to fully support the investigation. An RRAM compact model is also exploited to estimate the physical properties of the conductive filament and of the dielectric barrier from simple I–V data. These tools are combined together to prove the existence of a direct statistical relation between the reset conditions, the volume of the dielectric barrier created during the reset operation and the average number of active traps contributing to the RTN.