The practical deployment of massive multiple-input multiple-output (MIMO) in future fifth generation (5G) wireless communication systems is challenging due to its high hardware cost and power consumption. One promising solution to address this challenge is to adopt the low-resolution analog-to-digital converter (ADC) architecture. However, the practical implementation of such architecture is challenging due to the required complex signal processing to compensate the coarse quantization caused by low-resolution ADCs. Therefore, few high-resolution ADCs are reserved in the recently proposed mixed-ADC architecture to enable low-complexity transceiver algorithms. In contrast to previous works over Rayleigh fading channels, we investigate the performance of mixed-ADC massive MIMO systems over the Rician fading channel, which is more general for the 5G scenarios like Internet of Things (IoT). Specially, novel closed-form approximate expressions for the uplink achievable rate are derived for both cases of perfect and imperfect channel state information (CSI). With the increasing Rician $K$-factor, the derived results show that the achievable rate will converge to a fixed value. We also obtain the power-scaling law that the transmit power of each user can be scaled down proportionally to the inverse of the number of base station (BS) antennas for both perfect and imperfect CSI. Moreover, we reveal the trade-off between the achievable rate and energy efficiency with respect to key system parameters including the quantization bits, number of BS antennas, Rician $K$-factor, user transmit power, and CSI quality. Finally, numerical results are provided to show that the mixed-ADC architecture can achieve a better energy-rate trade-off compared with the ideal infinite-resolution and low-resolution ADC architectures.

Performance Analysis of Mixed-ADC Massive MIMO Systems over Rician Fading Channels

For 5G, it will be important to leverage the available millimeter wave spectrum. To achieve an approximately omnidirectional coverage with a similar effective antenna aperture compared with the state-of-the-art cellular systems, an antenna array is required at both the mobile and base stations. Due to the large bandwidth, the analog front-end of the receiver with a large number of antennas becomes especially power hungry. Two main solutions exist to reduce the power consumption: Hybrid BeamForming (HBF) and Digital BeamForming (DBF) with low resolution Analog to Digital Converters (ADCs). An HBF system can also be combined with low resolution ADCs. This paper compares the spectral and energy efficiency based on the RF-frontend configuration. A channel with multipath propagation is used. In contrast to previous publication, we take the spatial correlation of the quantization noise into account. We show that the low resolution ADC DBF is robust to small Automatic Gain Control (AGC) imperfections. We showed that in the low SNR regime, the performance of DBF even with 1–2 bit resolution outperforms HBF. If we consider the relationship of spectral and energy efficiency, DBF with 3–5 bit resolution achieves the best ratio of spectral efficiency per power consumption of the RF receiver frontend over a wide SNR range. The power consumption model is based on components reported in the literature.

Achievable Rate and Energy Efficiency of Hybrid and Digital Beamforming Receivers With Low Resolution ADC

An on-chip resonator is designed and fabricated using a standard 0.13- $\mu \text{m}$ SiGe technology for millimeter-wave applications. The designed resonator is based on a unique structure, which consists of two broadside-coupled meander lines with opposite orientation. The equivalent $LC$ circuit of the resonator is given, while the impact of the structure on the resonance frequencies is investigated. Using this structure along with capacitors, a compact bandpass filter (BPF) is also designed and fabricated. The measured results show that the resonator can generate a resonance at 57 GHz with the attenuation better than 13.7 dB, while the BPF has a center frequency at 31 GHz and a insertion loss of 2.4 dB. The chip size of both the resonator and the BPF, excluding the pads, is only 0.024 mm2 ( $0.09 \times 0.27$ mm $^{2})$ .

A Broadside-Coupled Meander-Line Resonator in 0.13- $\mu \text{m}$ SiGe Technology for Millimeter-Wave Application

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS Editor-in-Chief

This paper presents a fully integrated eight-way power-combining amplifier for 110-134-GHz applications in an advanced 90-nm silicon-germanium HBT technology. The eight-way amplifier is implemented using four-stage common-emitter single-ended power amplifiers (PAs) as building blocks, and reactive λ/4 impedance transformation networks are used for power combining. The single-ended PA breakout has a small-signal gain of 20 dB at 116 GHz, and saturation output power ( Psat) of 12.5-13.8 dBm at 114-130 GHz. The eight-way power-combining PA achieves a small-signal gain of 15 dB at 116 GHz, and Psat of 20-20.8 dBm at 114-126 GHz with a power-added efficiency of 7.6%-6.3%. The eight-way amplifier occupies 4.95 mm
 2
 (including pads) and consumes a maximum current of 980 mA from a 1.6-V supply. To our knowledge, this is the highest power silicon-based D-band amplifier to date.

/pdf/a-110-134-ghz-sige-amplifier-with-peak-output-power-of-100-51cr5t8w8a.pdf

A 110–134-GHz SiGe Amplifier With Peak Output Power of 100–120 mW

In this paper, low phase-noise, low-power, and compact oscillators are demonstrated at the millimeter-wave region based on differential transmission lines (DTLs) loaded with metamaterial resonators. There are two types of metamaterial resonators explored: split-ring resonators (SRRs) and complementary split-ring resonators (CSRRs). By creating a sharp stopband at the resonance frequency from a loaded SRR or CSRR, the backward electrical-magnetic (EM) wave is reflected to couple with the forward EM wave to form a standing EM wave in the DTL host, which results in a high- $Q$ and low-loss millimeter-wave resonator with stable EM energy stored. The resulting DTL-SRR and DTL-CSRR resonators are deployed for designs of millimeter-wave oscillators in 65-nm CMOS. The measurement results show that one DTL-SRR-based oscillator works at 76 GHz with power consumption of 2.7 mW, phase noise of $-{\hbox{108.8 dBc/Hz}}$ at 10-MHz offset, and figure-of-merit (FOM) of $-{\hbox{182.1 dBc/Hz}}$ , which is 4 dB better than that of a 76-GHz standing-wave oscillator implemented on the same chip. Moreover, another DTL-CSRR-based oscillator works at 96 GHz with power consumption of 7.5 mW. Compared to the existing oscillators with an LC-tank-based resonator, the DTL-CSRR oscillator has much lower phase noise of $- {\hbox{111.5 dBc/Hz}}$ at 10-MHz offset and a FOM of $- {\hbox{182.4 dBc/Hz}}$ .

Design of High- $Q$ Millimeter-Wave Oscillator by Differential Transmission Line Loaded With Metamaterial Resonator in 65-nm CMOS

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved.

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A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

An on-chip metamaterial resonator is demonstrated in 65 nm CMOS at 80 GHz for millimetre-wave integrated circuit (MMIC) applications. The resonator is based on a differential metamaterial transmission-line (T-line) loaded with a split ring resonator (SRR), which can enhance the EM energy coupling and further improve the quality factor (Q). Measurement results indicate that the proposed differential SRR (DSRR) T-line shows a sharp stopband with maximum 35 dB rejection. Moreover, the metamaterial property of the DSRR T-line is validated from the measurement results. It is the first on-chip demonstration of a millimetre-wave metamaterial resonator in 65 nm CMOS, which can be integrated for a low-noise oscillator and high-Q filter design in a 100 GHz MMIC communication system.

/pdf/80-ghz-on-chip-metamaterial-resonator-by-differential-2fcgy4d8i6.pdf

80 GHz on-chip metamaterial resonator by differential transmission line loaded with split ring resonator

This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 μm × 210 μm with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high- Q passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34- mm2 chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56- mm2 chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 ~ 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.

https://dr.ntu.edu.sg/bitstream/10356/103285/2/tmtt13_receiver%20%282%29.pdf

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

A 96-GHz CMOS oscillator is demonstrated in this brief with the use of a high-Q metamaterial resonator. The proposed metamaterial resonator is constructed by a differential transmission line (T-line) loaded with complementary split-ring resonator engraved on the T-line. A negative real part of permittivity, i.e., , is observed near the resonance frequency, which introduces a sharp stopband and, thus, leads to a high-Q resonance. This brief is the first in literature to explore CMOS on-chip metamaterial resonator for oscillator design at the millimeter-wave frequency region. Compared with the existing oscillators with a LC-tank-based resonator at around 100 GHz, the proposed 96-GHz oscillator with high- metamaterial resonator shows much lower phase noise of 111.5 dBc/Hz at 10-MHz offset and figure-of-merit of 182.4 dBc/Hz.

/pdf/a-96-ghz-oscillator-by-high-q-differential-transmission-line-4vke0l533u.pdf

Deyun Cai

Papers

Design of High- $Q$ Millimeter-Wave Oscillator by Differential Transmission Line Loaded With Metamaterial Resonator in 65-nm CMOS

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

80 GHz on-chip metamaterial resonator by differential transmission line loaded with split ring resonator

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

A 96-GHz Oscillator by High- $Q$ Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS