Showing papers by "Dominique Drouin published in 2019"

Uprooting defects to enable high-performance III–V optoelectronic devices on silicon

Abstract: The monolithic integration of III-V compound semiconductor devices with silicon presents physical and technological challenges, linked to the creation of defects during the deposition process. Herein, a new defect elimination strategy in highly mismatched heteroepitaxy is demonstrated to achieve a ultra-low dislocation density, epi-ready Ge/Si virtual substrate on a wafer scale, using a highly scalable process. Dislocations are eliminated from the epilayer through dislocation-selective electrochemical deep etching followed by thermal annealing, which creates nanovoids that attract dislocations, facilitating their subsequent annihilation. The averaged dislocation density is reduced by over three orders of magnitude, from ~108 cm-2 to a lower-limit of ~104 cm-2 for 1.5 µm thick Ge layer. The optical properties indicate a strong enhancement of luminescence efficiency in GaAs grown on this virtual substrate. Collectively, this work demonstrates the promise for transfer of this technology to industrial-scale production of integrated photonic and optoelectronic devices on Si platforms in a cost-effective way.

A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon

Abstract: III-V solar cell cost reduction and direct III-V/Si integration can both be realized by depositing a thin layer of high-quality Ge on relatively low-cost Si substrates. However, direct epitaxial growth of Ge on Si substrates is difficult due to the 4% lattice mismatch between the film and the substrate. Threading dislocations (TDs) introduced within the Ge layer have a detrimental effect on device performances. The goal of this research is to address the perennial need to minimize the defect density of Ge epilayers grown on a Si substrate. We seek to accommodate the effects of the lattice mismatch by introducing a porous Si interface layer to intercept dislocations and prevent them from reaching the active layers of the device. The porous Si layer is formed through dislocation-selective electrochemical deep etching and thermal annealing. The porous layer created beneath the top Ge layer can both act as dislocation traps and as a soft compliant substrate, which displays high flexibility. Transmission electron microscopy (TEM) analysis of the Ge/porous Si interface shows that the lattice mismatch strain of the Ge films was almost relaxed. The surface roughness of this modified Ge/Si substrate has been reduced using chemical mechanical polishing (CMP) process to fulfil the requirements for epitaxy of III-V alloys. Finally, we present simulation results exploring the effect of threading dislocations on device performance.

Observation of Highly Nonlinear Resistive Switching of Al2O3/TiO2-x Memristors at Cryogenic Temperature (1.5 K).

Abstract: In this work, we investigate the behavior of Al2O3/TiO2-x cross-point memristors in cryogenic environment. We report successful resistive switching of memristor devices from 300 K down to 1.5 K. The I-V curves exhibit negative differential resistance effects between 130 and 1.5 K, attributed to a metal-insulator transition (MIT) of the Ti4O7 conductive filament. The resulting highly nonlinear behavior is associated to a maximum ION/IOFF ratio of 84 at 1.5 K, paving the way to selector-free cryogenic passive crossbars. Finally, temperature-dependant thermal activation energies related to the conductance at low bias (20 mV) are extracted for memristors in low resistance state, suggesting hopping-type conduction mechanisms.

Source Separation Using Sensor's Frequency Response: Theory and Practice on Carbon Nanotubes Sensors.

Abstract: Nowadays, there is an increased demand in integrated sensors for electronic devices. Multi-functional sensors provide the same amount of data using fewer sensors. Carbon nanotubes are non-selectively sensitive to temperature, gas and strain. Thus, carbon nanotubes are perfect candidates to design multi-functional sensors. In our study, we are interested in a dual humidity-temperature sensor. Here, we present a novel method to differentiate at least two sources using the sensor’s frequency responses based on multiwall carbon nanotubes sensors. The experimental results demonstrate that there are temperature- or moisture-invariant frequencies of the impedance magnitude, and their values depend on the sensor’s geometry. The proposed measurement model shows that source-invariant frequencies of the phase can be also determined. In addition, the source separation method is generalized to other materials or sources enabling multi-functional sensors for environment monitoring.

Ag Diffusion Control Through Sn on a Sequential Plating-Based Bumping Process

Abstract: In this paper, we present our investigations on sequential plating for a low-cost bumping process. Following the demonstration of this process for low Ag concentration (1.4 wt%), we aimed this study on increase Ag concentration to 3 wt% and investigate its impact on Ag diffusion and intermetallics compound formation. Moreover, we created a Ag concentration gradient within the same bump in order to benefit from both favorable effects of low and high Ag concentration on the solder. To this end, we plated different metal sequences to form bumps with 90 µm and 75 µm of diameter and height respectively. The fabricated bumps were characterized, after a cross-sectional preparation, through SEM and EDS analysis to reveal the effects of the reflow profile and the use of a barrier on the Ag diffusion, as well as, the IMC formation.

Multi-physics Modelling and Experimental Investigation – An Original Approach for Laser-Dicing/Grooving Process Optimization

Abstract: The highly complex technology requirements of today's integrated circuits (ICs), lead to the increasingly use of several materials types such as metal structures, brittle dielectrics, porous low-k and ultra-low-k materials which are used in both front-end-of-line (FEOL) and back-end-of-line (BEOL) process for wafer manufacturing. In order to singulate chips from wafers, a critical laser-grooving process, prior to blade dicing, is used to remove these layers of materials out of the dicing street. The combination of laser-grooving and blade dicing allows to reduce the potential risk of induced mechanical defects such micro-cracks, chipping, on the wafer top surface where circuitry is located. Nevertheless, challenges related to unexpected drawbacks on process such as efficiency, quality and reliability still remain. To maximize control of this critical process and reduce its undesirable effects, numerical models of nano-second laser pulsed and multi-stack material interaction have been developed. The modeling strategy using finite elements formalism is based on the convergence of two approaches, numerical and experimental Validation. To evaluate this interaction, several laser grooved samples were performed using IBM 14 nm technology node wafer and were correlated with finite elements modeling. Three different aspects were studied; phase change, thermo-mechanical and optical sensitive parameters. The numerical model makes it possible to simulate groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat-affected zone (HAZ) has been estimated as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a reasonable agreement between experiment and modeling results has been observed in terms of groove depth, width and HAZ

Laser grooving of multi stack material modeling: implementation of a high accuracy tool for laser-grooving and dicing application

Abstract: Laser grooving is a powerful method widely used in the semiconductor industry for chip singulation because of the advantages it provides, such as high grooves profile quality, lower mechanical stresses on devices. Nevertheless, challenges related to unexpected drawbacks on process such as efficiency, quality and reliability still remain. In order to maximize control of this critical process and reduce its undesirable effects, numerical models of nano-second laser pulsed and multistack material interaction have been developed. The modeling strategy using finite elements formalism is based on the convergence of two approaches, numerical and experimental characterizations. To evaluate this interaction, several laser grooved of multilayer samples Cu/SiO2, Al/SiO2, and complete state of the art back-end-of-line (BEOL) material stack were correlated with finite elements modeling. Three different aspects were studied; phase change, thermo-mechanical sensitive parameters as well as optical sensitive parameters. The mathematical model makes it possible to highlight a groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat-affected zone (HAZ) has been predicted as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a satisfying correlation between experiment and modeling results has been observed in terms of groove depth, width and HAZ.

FPGA-based Multi-Chip Module for High-Performance Computing

Abstract: Current integration, architectural design and manufacturing technologies are not suited for the computing density and power efficiency requested by Exascale computing. New approaches in hardware architecture are thus needed to overcome the technological barriers preventing the transition to the Exascale era. In that scope, we report successful fabrication of first ExaNoDe's MCM prototypes dedicated to Exascale computing applications. Each MCM was composed of 2 Xilinx Zynq Ultrascale+ MPSoC, assembled on advanced 68.5 mm x 55 mm laminate substrates specifically designed and fabricated for the project. Acoustic microscopy, x-ray, cross-section and Thermo-Moire investigations revealed no voids, shorts, delamination, cracks or warpage issues. Two MCMs were mounted on a daughter board by FORTH for testing purposes. The DDR memories on the 4 SODIMMs of the daughter board were successfully tested by running extensive Xilinx memory tests with clock frequencies of 1866 MHz and 2133 MHz. All 4 FPGAs were programmed with the Xilinx integrated bit error ratio test (IBERT) tailored for this board for links testing. All intra-board high-speed links between all FPGAs were stable at 10 Gbps, even under the more demanding 31-bit PRBS (Pseudorandom Binary Sequence) tests.