Showing papers by "Fabrizio Lombardi published in 2014"

A low-power, high-performance approximate multiplier with configurable partial error recovery

Abstract: Approximate circuits have been considered for error-tolerant applications that can tolerate some loss of accuracy with improved performance and energy efficiency. Multipliers are key arithmetic circuits in many such applications such as digital signal processing (DSP). In this paper, a novel approximate multiplier with a lower power consumption and a shorter critical path than traditional multipliers is proposed for high-performance DSP applications. This multiplier leverages a newly-designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved through a configurable error recovery by using different numbers of most significant bits (MSBs) for error reduction. The approximate multiplier has a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared to the Wallace multiplier, a 16-bit approximate multiplier implemented in a 28nm CMOS process shows a reduction in delay and power of 20% and up to 69%, respectively. It is shown that by utilizing an appropriate error recovery, the proposed approximate multiplier achieves similar processing accuracy as traditional exact multipliers but with significant improvements in power and performance.

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

Abstract: Reliability is fast becoming a major concern due to the nanometric scaling of CMOS technology. Accurate analytical approaches for the reliability evaluation of logic circuits, however, have a computational complexity that generally increases exponentially with circuit size. This makes intractable the reliability analysis of large circuits. This paper initially presents novel computational models based on stochastic computation; using these stochastic computational models (SCMs), a simulation-based analytical approach is then proposed for the reliability evaluation of logic circuits. In this approach, signal probabilities are encoded in the statistics of random binary bit streams and non-Bernoulli sequences of random permutations of binary bits are used for initial input and gate error probabilities. By leveraging the bit-wise dependencies of random binary streams, the proposed approach takes into account signal correlations and evaluates the joint reliability of multiple outputs. Therefore, it accurately determines the reliability of a circuit; its precision is only limited by the random fluctuations inherent in the stochastic sequences. Based on both simulation and analysis, the SCM approach takes advantages of ease in implementation and accuracy in evaluation. The use of non-Bernoulli sequences as initial inputs further increases the evaluation efficiency and accuracy compared to the conventional use of Bernoulli sequences, so the proposed stochastic approach is scalable for analyzing large circuits. It can further account for various fault models as well as calculating the soft error rate (SER). These results are supported by extensive simulations and detailed comparison with existing approaches.

Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs

Abstract: Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation

Abstract: Energy consumption is a major concern in nanoscale CMOS ICs; the power-Off operational mode and low-voltage circuits have been proposed to alleviate energy dissipation Static random access memories (SRAMs) are widely used in today's chips; nonvolatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power- On/Off speeds Nonvolatile operation is usually accomplished by the use of a resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for nonvolatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as “Instant-on”) This paper presents a novel NVSRAM circuit for “Instant-on” operation and evaluates its performance at nanometric feature sizes The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an oxide resistive RRAM circuit (1T1R), thus making a 7T1R scheme The proposed cell offers better nonvolatile performance (in terms of operations such as “Store,” “Power-down,” and “Restore”) when compared with existing nonvolatile cells The scenario of multiple-context configuration is also analyzed Figures of merit such as energy, operational delay, and area are also substantially improved, making the proposed design a better scheme for “Instant-on” operation

Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset

Abstract: Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset). The proposed design is referred to as TDICE and uses transistors to block the paths that connect a node to the next node in the feedback loop of the memory cell circuit. The use of these transistors hardens the cell to tolerate a single event with a multiple-node upset at a large value of critical charge. Extensive simulation results are provided to assess TDICE with respect to traditional circuit figures of merit such as area, power consumption, and delay as well as PVT variations. The simulation results show that, at the expense of an increased area for the additional transistors, TDICE shows a nearly complete tolerance to a single event with a multiple-node upset.

A novel design of a memristor-based look-up table (LUT) for FPGA

Abstract: This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore, it addresses the prevalent problems associated with nano crossbars, such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns, while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition, the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations.

A memristor-based TCAM (ternary content addressable memory) cell

Abstract: This paper presents a Ternary Content Addressable Memory (TCAM) cell that employs memristors as storage element. The TCAM cell requires two memristors in series to perform the traditional memory operations (read and write) as well as the search and matching operations for TCAM; this memory cell is analyzed with respect to different features (such as memristance range and voltage threshold) of the memristors to process fast and efficiently the ternary data. A comprehensive simulation based assessment of this cell is pursued by HSPICE. Comparison with other memristor-based CAMs as well as CMOS-based TCAMs shows that the proposed cell offers significant advantages in terms of power dissipation, reduced transistor count and search/match operation performance.

A memristor-based LUT for FPGAs

Abstract: This paper presents a memristor-based Look-Up Table (LUT) for FPGAs. The proposed memory utilizes memristors as storage elements and NMOS transistors for selection. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation for both the word and bit lines. Also, it requires a RESTORE pulse only for the READ 0 operation. The WRITE operation of the proposed method requires three power lines (+Vdd, -Vdd and Gnd) and a RESTORE pulse only for the READ 0 operation, thus accomplishing savings of 25% for both the number of power lines and READ time when compared to previous methods. The proposed LUT is simulated using LTSPICE and extensive simulation results are presented with respect to different operational features, such as normalized state parameter of the memristance, pulse width, LUT size and MOSFET feature size. These results show that the proposed scheme offers superior performance compared with other existing memristor-based schemes found in the technical literature for FPGAs.

Inexact floating-point adder for dynamic image processing

Abstract: Power has become a key constraint in current nanoscale integrated circuit design due to the increasing demands for mobile computing and a low carbon economy. As an emerging technology, an inexact circuit design offers a promising approach to significantly reduce both dynamic and static power dissipation for error tolerant applications. Although fixed-point arithmetic circuits have been studied in terms of inexact computing, floating-point arithmetic circuits have not been fully considered although require more power. In this paper, the first inexact floating-point adder is designed and applied to high dynamic range (HDR) image processing. Inexact floating-point adders are proposed by approximately designing an exponent subtractor and mantissa adder. Related logic operations including normalization and rounding modules are also considered in terms of inexact computing. Two HDR images are processed using the proposed inexact floating-point adders to show the validity of the inexact design. HDR-VDP is used as a metric to measure the subjective results of the image addition. Significant improvements have been achieved in terms of area, delay and power consumption. Comparison results show that the proposed inexact floating-point adders can improve power consumption and the power-delay product by 29.98% and 39.60%, respectively.

A New Comprehensive Model of a Phase Change Memory (PCM) Cell

Abstract: This paper presents a HSPICE macromodel of a phase change memory (PCM) cell. The proposed PCM macromodel consists of two interrelated models, i.e., the operational model and the drift model. The operational model simulates the holding voltage, the programming process, and the continuous change behavior of the PCM resistance (as corresponding to the amorphous and crystalline phases) by considering also the temperature profile and the crystalline fraction. Using these features, drift behaviors are assessed for the resistance and the threshold voltage; the parameter drifts occur when the cell is not been programmed, thus matching simulation with the operational characteristics observed experimentally in a PCM cell. An analysis of the drift behaviors is then presented. This analysis provides the basis by which an electrical-based framework can be used for simulation. The simulation results show that the plots of resistance and threshold voltage of the PCM cell during the modeled drift behaviors are very close to the experimental results. Moreover, selection of the parameters is based on PCM operational features, so the electrical characterization of the drift is simple, easy to simulate and intuitive.

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Abstract: The last few years have seen the development and fabrication of nanoscale circuits at high density and low power. Following a single-event upset (SEU), so-called soft errors due to internal and externally induced phenomena (such as α-particles and cosmic rays in adverse environments) have been reported during system operation; this is especially deleterious for storage elements such as flip-flops. To reduce the impact of a soft error on flip-flops, hardening techniques have been utilized. This paper proposes two new slave latches for improving the SEU tolerance of a flip-flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. When used in a flip-flop, the first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16% (9%) power consumption overhead at 32-nm feature size, as compared with the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple-node upset.

Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs

Abstract: This paper presents a new method for diagnosing (detection and location) multiple faults in an application-dependent interconnect of a SRAM-based FPGA. For fault detection, the proposed technique retains the original interconnect configuration and modifies the function of the LUTs using the new LUT programming function 1-Bit Sum Function (1-BSF); in addition, it utilizes features such as branches in the nets as well as the primary (unused) IOs of the FPGAs. The proposed method detects all possible stuck-at and bridging faults of all cardinalities in a single configuration; fault detection requires $1 + {\rm log}_{2}k$ test configurations for multiple stuck-at location and $2 + 2{\rm log}_{2}k$ additional test configurations to locate more than one pair-wise bridging faults (where $k$ denotes the maximum combinational depth of the FPGA circuit). Following detection, the locations of multiple faults are hierarchically identified using the walking-1 test set and an adaptive approach for the interconnect structure. Net ordering independence is accomplished by utilizing features such as the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. As validated by simulation on benchmark circuits, the proposed method scales extremely well for different Virtex FPGA families; this results in a significant reduction in the number of configurations for diagnosing multiple faults.

A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes

Abstract: This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

A memristor-based memory cell with no refresh

Abstract: This paper analyzes and improves the performance of a hybrid memory cell consisting of a memristor and ambipolar transistors. This work extends a previous design by efficiently biasing the memristor (as controlled by the ambipolar transistors), such that no refresh operation is now required. By utilizing macroscopic models, the features of the cell are characterized for the memory operations and no modification is needed to the cell circuit other than the memristor biasing scheme. A detailed treatment of the memory cell with respect to the new biasing scheme of the memristor is provided. Simulation results show that the proposed memory cell has superior performance compared with the previous memristor-based cell.

Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders

Abstract: This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults Extensive simulation results are also provided; different figures of merit such as area, power dissipation, gate depth, and coverage are assessed It is shown that the proposed decoder designs for ( n, k) t-bit error correcting OLS codes (k = 16 256; t = 2 5) have reasonable overhead; for example, the average area overhead of the proposed CED is 355 (236) % compared with an OLS decoder with no CED (ie, the previously reported CED scheme) However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation The proposed CED is applicable to both binary and nonbinary OLS codes; the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy

A system-level scheme for resistance drift tolerance of a multilevel phase change memory

Abstract: This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold resistances found by the proposed scheme drift with time, thus providing an efficient and viable approach when the number of levels increases. A detailed analysis of the proposed level separation and threshold resistance selection is pursued. The impact of different parameters (such as the write region and the number of cell in a row) is assessed with respect to the generation of the percentage accuracy. The proposed approach results in a substantial improvement in performance compared with existing schemes found in the technical literature.

HSPICE macromodel of a programmable metallization cell (PMC) and its application to memory design

Abstract: This paper presents a new HSPICE macromodel of a Programmable Metalization Cell (PMC). The electrical characteristics of a PMC are simulated by using a geometric model that considers the vertical and lateral growth/disolution of the metallic filament. The selection of the parameters is based on operational features, so the electrical characterization of the PMC is simple, easy to simulate and intuitive. The I-V and R-V plots of a PMC are generated at a very small error compared with experimental data; the proposed model also shows a small error for the relationship between the switching time and the pulse amplitude. The use of a PMC as resistive element in a crossbar memory is also presented; it is shown that a PMC-based crossbar offers substantial improvements over other resistive technologies.

Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming

Abstract: The carbon nanotube field-effect transistor (CNTFET) has been advocated as one of the possible alternatives to replace the MOSFET. Some of the likely defect types that may occur in its manufacturing process are the presence of undeposited CNTs and the change in CNT diameter. Existing simulation models are inadequate to assess the effect of undeposited CNTs, due to the limitation in representing these CNT defects for circuit-level simulation and the high execution complexity. In this paper, a new method to evaluate CNTFETs with uneven spacing between CNTs (such as due to undeposited CNTs as defects) for circuit-level simulation is proposed; it is based on an equivalence relationship in some key performance metrics (current and gate capacitance) between CNTFETs with evenly/unevenly positioned CNTs. This relationship requires the adjustment of different parameters of the CNTFET. Using existing CNTFET models (based on MATLAB and HSPICE), linear programming is utilized to find the values of the relevant parameters (number, pitch, doping level, and chirality) of the simulation tools. The equivalence relationship is then established for circuit-level simulation. Different performance metrics (delay and energy) are presented for a five-stage fan-out-of-four inverter chain, under the conditions of evenly and unevenly positioned CNTs in the CNTFET. Computational requirements (such as simulation time and memory usage) of the proposed approach are reported; it is shown that the equivalence relation by adjusting the required parameters and the circuit-level evaluation of the CNTFET is computationally possible at a modest error (6% on average).

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction

Abstract: This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.

FDSOI SRAM cells for low power design at 22nm technology node

Abstract: The silicon-on-insulator (SOI) MOS as an alternative to the bulk (silicon-based M circuits for applications requiring low-voltag operation. Fully depleted SOI (FDSOI) ben current driven ability; so, this techn advantageous features, such as steep characteristics and small short channel ef presents a comprehensive assessment of differ Random Access Memory) cells utilizing diff transistors (i.e. 8 and 9). These cells are eval for different performance metrics (such as stability, critical charge, power consumption voltage threshold variation) at the 22nm techn

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

Abstract: This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.

New 4T-based DRAM cell designs

Abstract: Dynamic Random Access Memories (DRAM) are widely used in processor design. Different cells have been proposed in the past to overcome concerns associated with low retention time, degradation in performance due to process variations and susceptibility to soft errors. This paper proposes two novel DRAM cells (referred to as 4TI and 4T1D) that utilize the techniques of gated diode and forward body-biasing to overcome the above issues. The designs of these cells are evaluated by HSPICE simulation; different figures of merits (such as Read delay, Write delay, retention time, power dissipation, critical charge and layout area) are assessed and a comparative analysis of the proposed cells with existing cells is pursued. The 4TI cell achieves the best power dissipation, while the 4T1D achieves the best retention time, the highest critical charge and the least average Read delay. An extensive simulation based evaluation of process variations is also presented to confirm that using static and Monte Carlo based analysis, the proposed cells are likely to be less affected by process variations (in threshold voltage and effective channel length) than the other cells found in the technical literature.

An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior

Abstract: This paper proposes a new macro into account the threshold switching and the r processes in addition to the drift behavior o Memory (PCM). Simulation results are prov and drift behaviors; they show that the propos very accurate at a small error when compare experimental devices. A sensitivity analysis of also performed to show its operation with res variations. The model is suitable for circuit PCM devices. Index term – Phase-change memory, threshol recovery, modeling