Progress in the production and modification of PVDF membranes

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

/pdf/review-semiconductor-piezoresistance-for-microsystems-2i2jehwa4g.pdf

Review: Semiconductor Piezoresistance for Microsystems

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

https://www.pnas.org/content/pnas/105/48/18675.full.pdf

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

Moore's law: the future of Si microelectronics

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

For both n and pMOSFETs, this paper confirms via controlled wafer bending experiments and physical modeling the superiority of uniaxial over biaxial stressed Si and Ge MOSFETs. For uniaxial stressed p-MOSFETs, valence band warping creates favorable in and out-of-plane conductivity effective masses resulting in significantly larger hole mobility enhancement at low strain and high vertical field. For process-induced uniaxial stressed n-MOSFETs, a significant performance advantage results from a smaller threshold voltage shift due to less bandgap narrowing and the gate also being strained.

Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

Hole transport in the p-type metal-oxide-semiconductor field-effect-transistor (p-MOSFET) inversion layer under arbitrary stress, surface, and channel orientation is investigated by employing a six-band k∙p model and finite difference formalism. The piezoresistance coefficients are calculated and measured at stresses up to 300MPa via wafer-bending experiments for stresses of technological importance: uniaxial and biaxial stresses on (001) and (110) surface oriented p-MOSFETs with ⟨110⟩ and ⟨111⟩ channels. With good agreement in the measured and calculated small stress piezoresistance coefficients, k∙p calculations are used to give physical insights into hole mobility enhancement at large stress (∼3GPa). The results show that the maximum hole mobility is similar for (001)∕⟨110⟩, (110)∕⟨110⟩, and (110)∕⟨111⟩ p-MOSFETs under uniaxial stress, although the enhancement factor is different. Strong quantum confinement and a low density of states cause less stress-induced mobility enhancement for (110) p-MOSFETs. ...

Hole mobility in silicon inversion layers: Stress and surface orientation

The maximum electron and hole mobility enhancement for uniaxial process-induced strained silicon is modeled and experimentally measured using a flexure based 4-point wafer bending jig. The highest known uniaxial stress to date is introduced into the channel of MOSFETs (applied mechanical stress of ~1.0GPa on samples with initial process stress of 1GPa for a total channel stress of ~2Pa). The maximum mobility enhancement from uniaxial stress is found to be greater than ~4.0 and ~1.7 times for holes and electrons, respectively. The physics behind the strain enhanced mobility is explained and future cases of technological importance to the industry are investigated.

Future of Strained Si/Semiconductors in Nanoscale MOSFETs

We demonstrate for the first time that both SiGe and Ge channel with high-k/metal gate stack pMOSFETs show similar uniaxial stress enhanced drive current as Si which is expected from k.p calculations. We also demonstrate experimentally that pMOSFETs with strained quantum wells (QW) in the Si-Ge system exhibited high performance and low off-state leakage comparable to optimized gate stacks on Si. These results significantly hasten the feasibility of realizing SiGe or Ge channel pMOSFETs for 22 nm and beyond.

G. Sun

Papers

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

Hole mobility in silicon inversion layers: Stress and surface orientation

Future of Strained Si/Semiconductors in Nanoscale MOSFETs

High Performance pMOSFETs Using Si/Si 1-x Ge x /Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node