P
Pankaj Kalra
Researcher at University of California, Berkeley
Publications - 11
Citations - 106
Pankaj Kalra is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Metal gate & CMOS. The author has an hindex of 4, co-authored 11 publications receiving 104 citations.
Papers
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Proceedings ArticleDOI
Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
H.R. Harris,Pankaj Kalra,Prashant Majhi,Muhammad Mustafa Hussain,D. Q. Kelly,Jungwoo Oh,D. He,Casey Smith,Joel Barnett,Paul Kirsch,G. Gebara,Jesse S. Jur,Daniel J. Lichtenwalner,A. Lubow,Tso-Ping Ma,Guangyu Sung,Scott E. Thompson,Byoung Hun Lee,Hsing-Huang Tseng,Rajarao Jammy +19 more
TL;DR: In this paper, a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.
Proceedings ArticleDOI
High Performance pMOSFETs Using Si/Si 1-x Ge x /Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node
S. Suthram,Prashant Majhi,G. Sun,Pankaj Kalra,H.R. Harris,K.J. Choi,Dawei Heh,J. Oh,D. Q. Kelly,Rino Choi,Byung Jin Cho,Muhammad Mustafa Hussain,Casey Smith,S. Banerjee,Wilman Tsai,Scott E. Thompson,H.-H. Tseng,R. Jammy +17 more
TL;DR: In this article, the authors demonstrate that both SiGe and Ge channel with high-k/metal gate stack pMOSFETs show similar uniaxial stress enhanced drive current as Si which is expected from k.p calculations.
Proceedings ArticleDOI
Impact of flash annealing on performance and reliability of high-κ/metal-gate MOSFETs for sub-45 nm CMOS
Pankaj Kalra,Prashant Majhi,Dawei Heh,Gennadi Bersuker,Chadwin D. Young,N. Vora,R. Harris,Paul Kirsch,Rino Choi,Man Chang,Joonmyoung Lee,Hyunsang Hwang,Hsing-Huang Tseng,Rajarao Jammy,Tiehui Liu +14 more
TL;DR: In this paper, a detailed investigation of the effects of flash annealing on MOSFETs with Hf-based gate dielectric and metal gate electrodes is presented, and it is found to be compatible with the high-κ/metal gate stack.
Journal ArticleDOI
Modified NiSi ∕ Si Schottky Barrier Height by Nitrogen Implantation
Pankaj Kalra,Nikhil Vora,Prashant Majhi,P. Y. Hung,Hsing-Huang Tseng,Rajarao Jammy,Tiehui Liu +6 more
TL;DR: In this paper, a modified Schottky barrier height at the NiSi/Si(001) interface was shown to be reduced by passivation of dangling bonds at the interface to de-pin the Fermi level, axiotaxy texture and strain-induced barrier lowering.
Proceedings ArticleDOI
USJ Process Challenges for sub-45 nm CMOS
TL;DR: A review of the challenges associated with the formation of ultra-shallow junctions is presented in this paper, where it is shown that flash annealing retains high-κ/metal gate stack integrity, while achieving USJ benefits.