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Geoff Lowney
Researcher at Intel
Publications - 16
Citations - 4508
Geoff Lowney is an academic researcher from Intel. The author has contributed to research in topics: Compiler & Garbage collection. The author has an hindex of 10, co-authored 16 publications receiving 4240 citations.
Papers
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Journal ArticleDOI
Pin: building customized program analysis tools with dynamic instrumentation
Chi-Keung Luk,Robert Cohn,Robert Muth,Harish Patil,Artur Klauser,Geoff Lowney,Steven Wallace,Vijay Janapa Reddi,Kim Hazelwood +8 more
TL;DR: The goals are to provide easy-to-use, portable, transparent, and efficient instrumentation, and to illustrate Pin's versatility, two Pintools in daily use to analyze production software are described.
Journal ArticleDOI
Concurrent Collections
Zoran Budimlić,Michael G. Burke,Vincent Cavé,Kathleen Knobe,Geoff Lowney,Ryan R. Newton,Jens Palsberg,David M. Peixotto,Vivek Sarkar,Frank Schlimbach,Sagnak Tasirlar +10 more
TL;DR: The Concurrent Collections (CnC) programming model as discussed by the authors supports flexible combinations of task and data parallelism while retaining determinism, with the user providing high-level operations along with semantic ordering constraints that together form a CnC graph.
Journal ArticleDOI
Tarantula: a vector extension to the alpha architecture
Roger Espasa,Federico Ardanaz,Joel Emer,Stephen Felix,Julio Gago,Roger Gramunt,Isaac Hernandez,Toni Juan,Geoff Lowney,Matthew Mattina,André Seznec +10 more
TL;DR: Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads that fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, and achieves excellent "real-computation" per transistor and per watt ratios.
Patent
Implementing vector memory operations
Roger Espasa,Joel Emer,Geoff Lowney,Roger Gramunt,Santiago Galan,Toni Juan,Jesus Corbal,Federico Ardanaz,Isaac Hernandez +8 more
TL;DR: In this article, an address generator coupled with a register file is used to generate addresses for a vector memory operation, where the output slice includes addresses each corresponding to a separately addressable portion of a memory.
Proceedings ArticleDOI
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations
Nitish Srivastava,Hongbo Rong,Prithayan Barua,Guanyu Feng,Huanqi Cao,Zhiru Zhang,David H. Albonesi,Vivek Sarkar,Wenguang Chen,Paul Petersen,Geoff Lowney,Adam W. Herr,Christopher J. Hughes,Timothy G. Mattson,Pradeep Dubey +14 more
TL;DR: A language and compilation framework for productively generating high-performance systolic arrays for dense tensor kernels on spatial architectures, including FPGAs and CGRAs, which decouples a functional specification from a spatial mapping, allowing programmers to quickly explore various spatial optimizations for the same function.