G
Gregory W. Grynkewich
Researcher at Motorola
Publications - 23
Citations - 1047
Gregory W. Grynkewich is an academic researcher from Motorola. The author has contributed to research in topics: Magnetoresistive random-access memory & Layer (electronics). The author has an hindex of 14, co-authored 23 publications receiving 1024 citations. Previous affiliations of Gregory W. Grynkewich include Freescale Semiconductor.
Papers
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Journal ArticleDOI
Magnetoresistive random access memory using magnetic tunnel junctions
Saied N. Tehrani,Jon M. Slaughter,M. DeHerrera,B.N. Engel,Nicholas D. Rizzo,J. Salter,M. Durlam,Renu W. Dave,J. Janesky,Brian R. Butcher,K. Smith,Gregory W. Grynkewich +11 more
TL;DR: How the memory operates is described, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled the recent demonstration of a 1-Mbit memory chip.
Journal ArticleDOI
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
M. Durlam,P.J. Naji,A. Omair,M. DeHerrera,J. Calder,Jon M. Slaughter,B.N. Engel,Nicholas D. Rizzo,Gregory W. Grynkewich,Brian R. Butcher,Clarence J. Tracy,K. Smith,Kelly W. Kyler,J. Ren,J. Molla,W.A. Feil,R. Williams,Saied N. Tehrani +17 more
TL;DR: In this paper, a low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated.
Proceedings ArticleDOI
A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
M. Durlam,Peter K. Naji,A. Omair,M. DeHerrera,J. Calder,Jon M. Slaughter,Bradley N. Engel,Nicholas D. Rizzo,Gregory W. Grynkewich,Brian R. Butcher,Clarence J. Tracy,K. Smith,Kelly W. Kyler,J. Ren,J. Molla,B. Feil,R. Williams,Saied N. Tehrani +17 more
TL;DR: In this article, a low power 1 Mb Magnetoresistive Random Access Memory (MRAM) based on a 1-Transistor and 1-Magnetic Tunnel Junction (1T1MTJ) bit cell is demonstrated.
Proceedings ArticleDOI
A 0.18 /spl mu/m 4Mb toggling MRAM
M. Durlam,D. Addie,Johan Åkerman,Brian R. Butcher,P. Brown,J. Chan,M. DeHerrera,B.N. Engel,B. Feil,Gregory W. Grynkewich,J. Janesky,M. Johnson,Kelly W. Kyler,J. Molla,J. Martin,K. Nagel,J. Ren,Nicholas D. Rizzo,T. Rodriguez,L. Savtchenko,J. Salter,Jon M. Slaughter,K. Smith,J. J. Sun,M. Lien,K. Papworth,P. Shah,W. Qin,R. Williams,L. Wise,Saied N. Tehrani +30 more
TL;DR: In this paper, a low power 4Mb magnetoresistive random access memory (MRAM) with a new magnetic switching mode is presented for the first time, which is based on a 1-Transistor 1-Magnetic Tunnel Junction (1TIMTJ) bit cell.
Patent
Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
Gregory W. Grynkewich,Brian R. Butcher,Mark A. Durlam,Kelly W. Kyler,Charles A. Synder,Kenneth H. Smith,Clarence J. Tracy,Richard G. Williams +7 more
TL;DR: In this article, a memory element layer overlying a dielectric region was used to contact an electrically conductive layer over a magnetoelectronics element, forming a masking layer.