The efficiency of silicon solar cells has a large influence on the cost of most photovoltaics panels. Here, researchers from Kaneka present a silicon heterojunction with interdigitated back contacts reaching an efficiency of 26.3% and provide a detailed loss analysis to guide further developments.

Silicon heterojunction solar cell with interdigitated back contacts for a photoconversion efficiency over 26

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

We have achieved a certified 25.1% conversion efficiency in a large area (151.9 cm2) heterojunction (HJ) crystalline Si (c-Si) solar cell with amorphous Si (a-Si) passivation layer. This efficiency is a world record in a both-side-contacted c-Si solar cell. Our high efficiency HJ c-Si solar cells are investigated from the standpoint of the effective minority carrier lifetime (τe), and the impact of τe on fill factor (FF) is discussed. The τe measurements of our high efficiency HJ c-Si solar cells reveal that τe at an injection level corresponding to an operation point of maximum power is dominated by the carrier recombination at the a-Si/c-Si interface. By optimization of the process conditions, the carrier recombination at the a-Si/c-Si interface is reduced, which leads to an improvement of the FF by an absolute value of 2.7%, and a conversion efficiency of 25.1% has been achieved. These results indicate that the reduction of carrier recombination centers at the a-Si/c-Si interface should be one of the m...

Impact of carrier recombination on fill factor for large area heterojunction crystalline silicon solar cell with 25.1% efficiency

The global photovoltaic (PV) market is dominated by crystalline silicon (c-Si) based technologies with heavily doped, directly metallized contacts. Recombination of photo-generated electrons and holes at the contact regions is increasingly constraining the power conversion efficiencies of these devices as other performance-limiting energy losses are overcome. To move forward, c-Si PV technologies must implement alternative contacting approaches. Passivating contacts, which incorporate thin films within the contact structure that simultaneously supress recombination and promote charge-carrier selectivity, are a promising next step for the mainstream c-Si PV industry. In this work, we review the fundamental physical processes governing contact formation in c-Si. In doing so we identify the role passivating contacts play in increasing c-Si solar cell efficiencies beyond the limitations imposed by heavy doping and direct metallization. Strategies towards the implementation of passivating contacts in industrial environments are discussed. The development of passivating contacts holds great potential for enhancing the power conversion efficiency of silicon photovoltaics. Here, De Wolf et al. review recent advances in material design and device architecture, and discuss technical challenges to industrial fabrication.

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Passivating contacts for crystalline silicon solar cells

A wafer-based monocrystalline silicon photovoltaics road map: Utilizing known technology improvement opportunities for further reductions in manufacturing costs

Copper plating for 3D interconnects

A scalable generic Through Silicon Via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in Silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be ≪100mΩ. It is a via-last TSV process which is applicable to any silicon technology.

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O 3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

Large Area Copper Plated Silicon Solar Cell Exceeding 19.5% Efficiency

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions

Harold Philipsen

Papers

Copper plating for 3D interconnects

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

Large Area Copper Plated Silicon Solar Cell Exceeding 19.5% Efficiency

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping