International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

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Electrodynamics Of Continuous Media

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

Critical fluctuation of the order parameter in type-ii superconductors.

The silicon on thin buried oxide (SOTB) has the smallest V th variation among planar CMOS due to a low-dose channel. This study focuses on evaluating local variability components and searching for the dominant factor after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity is important to reduce both the global and local variations. The local V th variation A Vt was very small, ~ 1.0 and 0.7 mV·?m for NMOS and PMOS, respectively; however, additional unknown factors other than RDF still exist. Silicon-on-insulator thickness variation does not play a major role in ?V th , and the SOTB is scalable to less than 25 nm while maintaining small variability and, hence, low power consumption. The larger variability in NMOS compared to that in PMOS cannot be explained by conventional RDF but seems to be strongly related to channel doping.

Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

The Silicon on Thin BOX (SOTB) has the smallest Vth variation among planar CMOS due to low-dose channel. This study focused on identifying the remaining components after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity and body-thickness uniformity is the key to further reducing the variation. An often mentioned phenomenon, larger variability in NMOS than PMOS, cannot be explained by conventional RDF but is surely related to channel doping.

Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation

Thin drift layers were used to realize n-channel 4H-SiC IGBTs with an extremely low switching loss. The thickness of a drift layer was 60 μm, which was designed for a blocking voltage of 6.5 kV. An on-voltage of 5.4 V was obtained at a collector current of 100 A/cm2 and the specific differential on-resistance at 100 A/cm2 was 20 mΩcm2 at room temperature, indicating proper bipolar operation. A switching evaluation of the SiC IGBTs was performed with a bus voltage of 3.6 kV and a load current of 10 A, and a turn-off loss of 1.2 mJ was obtained. This turn-off loss is very small compared to the values in the current literatures, and was estimated to be an over 80% reduction. The series operation of thin-drift-layer 6.5 kV SiC IGBTs can ensure a lower switching loss than the single operation of higher blocking voltage devices in power conversion systems.

6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer

Evidence is given for the mechanism of hole-trap-related random telegraph noise (RTN) in reverse-biased junction leakage current occurring in the off-state of sub-micron scaled metal-oxide-semiconductor field-effect transistor (MOSFET). It was found that such RTN in junction leakage current, namely, variable junction leakage (VJL), is induced by applying hole-accumulation bias to the gate of the MOSFET. This result indicates that a hole captured in the gate oxide near the silicon surface influences the channel surface potential and causes fluctuation in generation-recombination (g-r) current generated at interface states. The fluctuation in g-r current is observed as VJL. It was also found that occurrence rate of VJL increases under hot-carrier stress. On the basis of these results, a model for VJL that can more concretely explain the mechanism of VJL quantitatively was developed.

Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor

The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or one hole, and its importance is recognised upon the aggressive scaling. However, the detailed nature of the charge trap remains to be investigated due to the difficulty to find out the exact device, which shows the RTN feature over statistical variations. Here, we show the RTN can be observed from virtually all devices at low temperatures, and provide a methodology to enable a systematic way to identify the bias conditions to observe the RTN. We found that the RTN was observed at the verge of the Coulomb blockade in the stability diagram of a parasitic Single-Hole-Transistor (SHT), and we have successfully identified the locations of the charge traps by measuring the bias dependence of the RTN.

/pdf/random-telegraph-noise-from-resonant-tunnelling-at-low-2otglhelps.pdf

Hiroyuki Yoshimoto

Papers

Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation

6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer

Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor

Random telegraph noise from resonant tunnelling at low temperatures.