J
Jason P. Campbell
Researcher at National Institute of Standards and Technology
Publications - 113
Citations - 1149
Jason P. Campbell is an academic researcher from National Institute of Standards and Technology. The author has contributed to research in topics: Negative-bias temperature instability & Gate oxide. The author has an hindex of 14, co-authored 107 publications receiving 976 citations.
Papers
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Journal ArticleDOI
Disease detection and management via single nanopore-based sensors.
Joseph E. Reiner,Arvind Balijepalli,Joseph W. F. Robertson,Jason P. Campbell,John S. Suehle,John J. Kasianowicz +5 more
TL;DR: This paper presents a probabilistic simulation of the response of the immune system to laser-spot assisted, 3D image analysis and shows the importance of knowing the number ofocytes in the blood stream.
Journal ArticleDOI
A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices
TL;DR: In this paper, a series resistance extraction method based on the ratio of two linear ID-VG measurements is proposed to extract the series resistance from a series of advanced CMOS devices.
Proceedings ArticleDOI
Random telegraph noise in highly scaled nMOSFETs
Jason P. Campbell,J. Qin,Kin P. Cheung,Liangchun Yu,John S. Suehle,Anthony S. Oates,Kuang Sheng +6 more
TL;DR: In this paper, the authors extracted the characteristic capture and emission time constants from RTN in highly scaled nMOSFETs and showed that they are inconsistent with the elastic tunneling picture dictated by the physical thickness of the gate dielectric (1.4 nm).
Patent
Electron spin resonance spectrometer and method for using same
TL;DR: An electron spin resonance spectrometer as mentioned in this paper includes a bridge to transmit an excitation frequency and to receive a signal frequency; a probe electrically connected to the bridge and comprising: a first conductor in electrical communication with the bridge, a shorting member, and a magnet disposed proximate to the probe.
Journal ArticleDOI
Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs
Z. Chbili,Asahiko Matsuda,Jaafar Chbili,Jason T. Ryan,Jason P. Campbell,Mhamed Lahbabi,Dimitris E. Ioannou,Kin P. Cheung +7 more
TL;DR: In this paper, the authors proposed a new defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures in SiC/SiO2 DMOSFETs.