Showing papers by "Jason S. Orcutt published in 2014"

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process

Abstract: An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process

Abstract: Based on a novel, “spoked-ring” active microcavity, we demonstrate optical modulators in an unmodified 45nm SOI CMOS process at 5Gbps with <5fJ/bit energy consumption; and filters with record thermal tuning efficiency of 2µW/GHz.

Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process.

Abstract: We present measurements on resonant photodetectors utilizing sub-bandgap absorption in polycrystalline silicon ring resonators, in which light is localized in the intrinsic region of a p+/p/i/n/n+ diode. The devices, operating both at λ=1280 and λ=1550 nm and fabricated in a complementary metal-oxide-semiconductor (CMOS) dynamic random-access memory emulation process, exhibit detection quantum efficiencies around 20% and few-gigahertz response bandwidths. We observe this performance at low reverse biases in the range of a few volts and in devices with dark currents below 50 pA at 10 V. These results demonstrate that such photodetector behavior, previously reported by Preston et al. [Opt. Lett.36, 52 (2011)], is achievable in bulk CMOS processes, with significant improvements with respect to the previous work in quantum efficiency, dark current, linearity, bandwidth, and operating bias due to additional midlevel doping implants and different material deposition. The present work thus offers a robust realization of a fully CMOS-fabricated all-silicon photodetector functional across a wide wavelength range.

Waveguide formation using cmos fabrication techniques

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

Integration of silicon photonics in bulk CMOS

Abstract: The first monolithic process flow integrating silicon photonics on operational bulk CMOS has been developed. Features include deep-trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables Tx/Rx operation while minimizing interconnect parasitics. With the addition of an external 1280nm source, a fully functional optical link (5Gb/s 2.8pJ/b), capable of wavelength division multiplexing, has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically-integrated Silicon-Germanium selective epitaxial growth based photodetector was developed.

Photonic Crystal Microcavities in a Microelectronics 45nm SOI CMOS Technology

Abstract: We demonstrate the first monolithically integrated linear photonic crystal microcavities in an advanced SOI CMOS microelectronics process (IBM 45nm 12SOI) with no in-foundry process modifications. The cavities were integrated into a standard microelectronics design flow meeting process design rules, and fabricated alongside transistors native to the process. We demonstrate both 1520nm wavelength and 1180nm cavity designs using different cavity implementations due to design rule constraints. For the 1520nm and 1180nm designs, loaded quality factors of 2,000 and 4,000 are measured, and intrinsic quality factors of 100,000 and 60,000 are extracted. We also demonstrate an evanescent coupling geometry which decouples the cavity and waveguide-coupling design.

Tolerance analysis for efficient MMI devices in silicon photonics

Abstract: Silicon is considered a promising platform for photonic integrated circuits as they can be fabricated in state-of-the-art electronics foundaries with integrated CMOS electronics. While much of the existing work on CMOS photonics has used directional couplers for power splitting, multimode interference (MMI) devices may have relaxed fabrication requirements and smaller footprints, potentially energy efficient designs. They have already been used as 1x2 splitters, 2x1 combiners in Quadrature Phase Shift Keying modulators, and 3-dB couplers among others. In this work, 3-dB, butterfly and cross MMI couplers are realized on bulk CMOS technology. Footprints from around 40um 2 to 200 um 2 are obtained. MMI tolerances to manufacturing process and bandwidth are analyzed and tested showing the robustness of the MMI devices.

Unidirectional chip-to-fiber grating couplers in unmodified 45nm CMOS Technology

Abstract: We propose and demonstrate the first asymmetric unidirectional grating couplers fabricated in a 45nm unmodified CMOS process Measured coupling efficiency from fiber-to-chip is ~40 %Simulations show g70% efficiency is achievable with same design

Optical modulator from standard fabrication processing

Abstract: An optical modulator is disclosed that includes an optical resonator structure. The optical resonator structure includes at least one non-linear portion, the at least one non-linear portion comprising at least one radial junction region. The at least one radial junction region is formed between at least first and second materials, respectively, having different electronic conductivity characteristics. A principal axis of the at least one radial junction region is oriented along a radius of curvature of the at least one non-linear portion. The optical modulator includes an optical waveguide that is coupled to the at least one non-linear portion of the optical resonator structure.

Method and structure providing a front- end- of- line and a back-end-of-line coupled waveguides

Abstract: An integrated structure and method of formation provide a lower level waveguide having a core of a first material and a higher level waveguide having a core of a second material and a coupling region for coupling the two waveguides together. The different core materials provided different coupled waveguides having different light loss characteristics.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

Abstract: We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process – the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

CMOS integrated Silicon Photonics - does it make sense?

Abstract: CMOS integrated Silicon Photonics offers a compact solution for a fully functional optical engine. The interdependence of optical and electrical components is discussed and arguments for a co-optimization of these components are given.

A monolithically-integrated chip-to-chip optical link in bulk CMOS

Abstract: A silicon-photonic link is monolithically-integrated in a bulk CMOS process for the first time. Deep-trench isolation enables polySi waveguide integration. PolySi resonant detectors remove the need for Ge integration. Split-diode design enables half-rate receivers, mitigating transistor speed limitations. An on-chip feedback loop locks the resonant defect detector to the laser wavelength, combating thermal upset. The 5 m optical link achieves 5 Gb/s at 3 pJ/b electrical and 13 pJ/b optical energy, in 0.18 μm (100 ps FO4) bulk CMOS memory periphery process.