J
Jatin Chhugani
Researcher at Intel
Publications - 81
Citations - 5008
Jatin Chhugani is an academic researcher from Intel. The author has contributed to research in topics: SIMD & Rendering (computer graphics). The author has an hindex of 28, co-authored 80 publications receiving 4728 citations. Previous affiliations of Jatin Chhugani include IBM & Johns Hopkins University.
Papers
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Proceedings ArticleDOI
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
Christopher J. Hughes,Radek Grzeszczuk,Eftychios Sifakis,Daehyun Kim,Sanjeev Kumar,Andrew Selle,Jatin Chhugani,Matthew J. Holliman,Yen-Kuang Chen +8 more
TL;DR: This work studies a set of three workloads that exemplify the span and complexity of physical simulation applications used in a production environment: fluid dynamics, facial animation, and cloth simulation, which are computationally demanding and can benefit greatly from the acceleration possible with large scale CMPs.
Proceedings ArticleDOI
Matrix factorizations at scale: A comparison of scientific data analytics in spark and C+MPI using three case studies
Alex Gittens,Aditya Devarakonda,Evan Racah,Michael F. Ringenburg,L. Gerhardt,Jey Kottalam,Jialin Liu,Kristyn Maschhoff,Shane Canon,Jatin Chhugani,Pramod Sharma,Jiyan Yang,James Demmel,Jim Harrell,Venkat Krishnamurthy,Michael W. Mahoney,Prabhat +16 more
TL;DR: In this article, the authors explore the trade-offs of performing linear algebra using Apache Spark compared to traditional C and MPI implementations on HPC platforms, and apply these methods to 1.6TB particle physics, 2.2TB and 16TB climate modeling and 1.1TB bioimaging data.
Proceedings ArticleDOI
Large-scale energy-efficient graph traversal: a path to efficient data-intensive supercomputing
TL;DR: This work shows that it can overcome constraints using a combination of efficient low-overhead data compression techniques to reduce transfer volumes along with latency-hiding techniques, resulting in over 6.6X performance improvements over state-of-the-art data transfer techniques, and almost an order of magnitude in energy savings.
Patent
System and method for memory bandwidth friendly sorting on multi-core architectures
Jatin Chhugani,Sanjeev Kumar,Anthony-Trung D. Nguyen,Yen-Kuang Chen,Victor W. Lee,William W. Macy +5 more
TL;DR: In this article, a tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node, and the completed output list in memory storage is a list of the fully sorted data.
Journal ArticleDOI
Atomic Vector Operations on Chip Multiprocessors
Sanjeev Kumar,Daehyun Kim,Mikhail Smelyanskiy,Yen-Kuang Chen,Jatin Chhugani,Christopher J. Hughes,Changkyu Kim,Victor W. Lee,Anthony D. Nguyen +8 more
TL;DR: The GLSC is proposed, which extends scatter-gather hardware to support atomic vector operations and provides an average performance improvement on a set of important RMS kernels of 54% for 4-wide SIMD.