Journal ArticleDOI
A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators
TLDR
A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed, thus enabling their application to an arbitrary modulator, and results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance.Abstract:
Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time sigma-delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD.read more
Citations
More filters
Journal ArticleDOI
Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey
TL;DR: A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.
Book
Analog-to-Digital Conversion
TL;DR: Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level, which makes it a reference for the experienced engineer.
Journal ArticleDOI
A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$ 74 dBFS THD in 125 MHz BW
TL;DR: In this article, a 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer.
Journal ArticleDOI
An 8.5 mW Continuous-Time $\Delta \Sigma $ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR
TL;DR: This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer, which achieves a figure of merit of 138 fJ/conv and is used to compensate for excess loop delay.
Journal ArticleDOI
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW
John G. Kauffman,Pascal Witte,Matthias Lehmann,Joachim Becker,Yiannos Manoli,Maurits Ortmanns +5 more
TL;DR: In this article, a single loop, third order continuous time ΔΣ modulator with an internal 4-bit quantizer sampled at 500 MHz with only an oversampling ratio of 10.
References
More filters
Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging
R.T. Baird,Terri S. Fiez +1 more
TL;DR: A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ data converters, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate.
Journal ArticleDOI
Excess loop delay in continuous-time delta-sigma modulators
TL;DR: In this article, the effect of excess loop delay on modulator dynamic range is studied through simulation for the standard double-integration (low pass) CT modulator and its equivalent fourth-order f/sub s/4 band pass circuit.
Journal ArticleDOI
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
TL;DR: In this paper, a third-order continuous-time /spl Sigma/spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 mm/sup 2/.
Journal ArticleDOI
Optimal parameters for /spl Delta//spl Sigma/ modulator topologies
TL;DR: A graph showing the maximal achievable performance of each topology as a function of the oversampling ratio is presented, offering a valuable help for the design of analog-to-digital converters.