A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A dry etching method and apparatus are described. A workpiece supports silicon nitride and silicon dioxide. The workpiece is exposed to a plasma containing at least one of sulfur hexafluoride and nitrogen trifluoride and ammonia to selectively remove the silicon nitride in relation to the silicon dioxide. In one feature, the plasma contains sulfur hexafluoride and ammonia. In another feature, the plasma contains nitrogen trifluoride and ammonia.

Selective etching method and apparatus

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.

Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane

Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Structure Incorporating Latch-Up Resistant Semiconductor Device Structures on Hybrid Substrates

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond.

Plasma Charge Accumulative Model in Quantitative FinFET Plasma Damage

A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30 A and a second poly-load resistor 30 B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12 . Both p-type and n-type impurity ions are implanted into the polysilicon layer 30 . An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20 . The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30 . Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors. The first and second poly-load resistors can have different implant dose to get the desired cut off temperatures.

Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor

A new method of suppressing short channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is described. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening. The silicon nitride layer is removed to form a gate electrode wherein the delta-channel implant underlies the gate electrode. Thereafter, lightly doped regions and source and drain regions are formed within the semiconductor substrate associated with the gate electrode to complete fabrication of the integrated circuit device.

Method of delta-channel in deep sub-micron process

A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.

7nm FinFET Plasma Charge Recording Device

Temperature dependent activation energy (E a ) has been observed for backend low-к (LK) and extreme LK (ELK) dielectric TDDB. We experimentally demonstrated that the charge transport through the LK/ELK is dominated by the Poole-Frenkel mechanism, even in the low E-field, and Cu-ion diffusion occurs at a later stage of stressing, which is more probable at high temperatures and in sub-65nm (40–28nm) technologies with ELK dielectric. Hence, the TDDB lifetime prediction at nominal operating conditions on the basis of elevated temperature experiments should take the temperature dependent E a into consideration. Based on the power-law relation between current and stress time at different temperatures, a comprehensive breakdown model of LK/ELK is proposed, which describes LK/ELK temperature dependent TDDB activation energy is associated with both the trap creation and the ion diffusion processes.

Jiaw-Ren Shih

Papers

Plasma Charge Accumulative Model in Quantitative FinFET Plasma Damage

Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor

Method of delta-channel in deep sub-micron process

7nm FinFET Plasma Charge Recording Device

A comprehensive breakdown model describing temperature dependent activation energy of low-к/extreme low-к dielectric TDDB