A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A dry etching method and apparatus are described. A workpiece supports silicon nitride and silicon dioxide. The workpiece is exposed to a plasma containing at least one of sulfur hexafluoride and nitrogen trifluoride and ammonia to selectively remove the silicon nitride in relation to the silicon dioxide. In one feature, the plasma contains sulfur hexafluoride and ammonia. In another feature, the plasma contains nitrogen trifluoride and ammonia.

Selective etching method and apparatus

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.

Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane

Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Structure Incorporating Latch-Up Resistant Semiconductor Device Structures on Hybrid Substrates

As one of the most promising embedded non-volatile storage solutions for advanced CMOS modules, resistive random access memory’s (RRAM) applications depend highly on its cyclability. Through detailed analysis, links have been found between noise types, filament configurations and the occurrence of reset failure during cycling test. In addition, a recovery treatment is demonstrated to restore the cyclability of RRAM. An early detection circuit for vulnerable cells in an array is also proposed for further improving the overall endurance of an RRAM array. Lifetime of RRAM can be extended to over 10 k cycles without fail bits in an array.

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An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array.

A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.

On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes

The present invention provides a method for forming shallow trench isolation of semiconductor integrated circuit, which is suitable for a semiconductor substrate having N-well/P-well areas. The method comprises the steps of: forming a shielding layer on the surface of the semiconductor substrate; forming a first trench on the semiconductor substrate via the shielding layer, so as to define a portion to be formed with the P-well/N-well isolation area; forming a spacer on the side wall of the first trench; using the spacer as a mask to etch the semiconductor substrate downwardly until a predetermined depth is reached, thereby forming a second trench; and removing the spacer and forming a shallow trench isolation object in the first and second trenches.

Method for forming shallow trench isolation

A novel in situ imaging solution and detectors array for the focused electron beam (e-beam) are the first time proposed and demonstrated. The proposed in-tool, on-wafer e-beam detectors array features full FinFET CMOS logic compatibility, compact 2 T pixel structure, fast response, high responsivity, and wide dynamic range. The e-beam imaging pattern and detection results can be further stored in the sensing/storage node without external power supply, enabling off-line electrical reading, which can be used to rapidly provide timely feedback of the key parameters of the e-beam on the projected wafers, including dosage, accelerating energy, and intensity distributions.

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Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology.

An in-tool, on-wafer detectors’ array for monitoring deep ultraviolet (DUV) light is proposed and demonstrated in this work. The proposed electronic layer detectors array (ELDA) features FinFET CMOS compatibility and compact pixel structure. Its minimum pixel pitch can reach 0.7 $\mu \text{m}$ , enabling the realization of high spatial resolution array. Most importantly, the sensing results from DUV exposure can be stored in the in-pixel storage node for days without external power supply, providing offline electrical nondestructive measurement and readout.

Jiaw-Ren Shih

Papers

An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array.

On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes

Method for forming shallow trench isolation

Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology.

Battery-Less Electronic Layer Detectors Array (ELDA) for In-Tool DUV Detection by FinFET CMOS Technology