Jinseong Heo

TL;DR: It is shown that for a graphene-silicon interface, Fermi-level pinning can be overcome and a triode-type device with a variable barrier, a “barristor,” can be made and used to create devices such as inverters.

TL;DR: A two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack, demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-Terminal memories.

TL;DR: This work demonstrated a highly sensitive photodetector with a MoS2/h-BN/graphene heterostructure, by inserting a h-BN insulating layer between graphene electrode and MoS 2 photoabsorber.

TL;DR: In this paper, a single-layer graphene (SLG) ferroelectric field effect transistor (FFET) was demonstrated to be optically visible on a lead-zirconate-titanate (PZT) substrate.

TL;DR: In this paper, a gate oxide on a conductive substrate is configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metal and on the first surface, and a source electrode and a drain electrode on both edges of the channel layer.