E
Edward W. Kiewra
Researcher at IBM
Publications - 75
Citations - 1614
Edward W. Kiewra is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & CMOS. The author has an hindex of 20, co-authored 75 publications receiving 1590 citations. Previous affiliations of Edward W. Kiewra include GlobalFoundries.
Papers
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Proceedings ArticleDOI
A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications
Solomon Assefa,Steven M. Shank,William M. J. Green,Marwan H. Khater,Edward W. Kiewra,Carol Reinholm,Swetha Kamlapurkar,Alexander V. Rylyakov,Clint L. Schow,Folkert Horst,Huapu Pan,Teya Topuria,Philip M. Rice,Douglas M. Gill,Jessie Rosenberg,Tymon Barwicz,Min Yang,Jonathan E. Proesel,Jens Hofrichter,Bert Jan Offrein,Xiaoxiong Gu,Wilfried Haensch,John J. Ellis-Monaghan,Yurii A. Vlasov +23 more
TL;DR: The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated.
Journal ArticleDOI
Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits
Benjamin G. Lee,Alexander V. Rylyakov,William M. J. Green,Solomon Assefa,Christian W. Baks,Renato Rimolo-Donadio,Daniel M. Kuchta,Marwan H. Khater,Tymon Barwicz,Carol Reinholm,Edward W. Kiewra,Steven M. Shank,Clint L. Schow,Yurii A. Vlasov +13 more
TL;DR: This work shows that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths, and validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations.
Journal ArticleDOI
High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High- $\kappa$ Gate Dielectrics and $\alpha$ -Si Passivation
Yuan-Chen Sun,Edward W. Kiewra,J. P. de Souza,J.J. Bucchignano,Keith E. Fogel,D. K. Sadana,Ghavam G. Shahidi +6 more
TL;DR: In this article, both short and long buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated.
Journal ArticleDOI
Inversion mode n-channel GaAs field effect transistor with high-k/metal gate
J. P. de Souza,Edward W. Kiewra,Yuan-Chen Sun,Alessandro C. Callegari,D. K. Sadana,Ghavam G. Shahidi,David J. Webb,J. Fompeyrine,Roland Germann,C. Rossel,Chiara Marchiori +10 more
TL;DR: In this paper, a thin amorphous Si (a-Si) cap was used to passivate metal-oxide-semiconductor field effect transistors (MOSFETs).
Patent
Process of enclosing via for improved reliability in dual damascene interconnects
TL;DR: In this paper, a dual damascene process was proposed to enclose a via in a dual-damascene fashion. But the barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.