An electronic–photonic microprocessor chip manufactured using a conventional microelectronics foundry process is demonstrated; the chip contains 70 million transistors and 850 photonic components and directly uses light to communicate to other chips. The rapid transfer of data between chips in computer systems and data centres has become one of the bottlenecks in modern information processing. One way of increasing speeds is to use optical connections rather than electrical wires and the past decade has seen significant efforts to develop silicon-based nanophotonic approaches to integrate such links within silicon chips, but incompatibility between the manufacturing processes used in electronics and photonics has proved a hindrance. Now Chen Sun et al. describe a 'system on a chip' microprocessor that successfully integrates electronics and photonics yet is produced using standard microelectronic chip fabrication techniques. The resulting microprocessor combines 70 million transistors and 850 photonic components and can communicate optically with the outside world. This result promises a way forward for new fast, low-power computing systems architectures. Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

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Single-chip microprocessor that communicates directly using light

As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

A role for graphene in silicon-based semiconductor devices

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

System and methods for converting planar design to FinFET design

A phased-array transmitter (TX) for multi-Gb/s non-line-of-sight links in the four frequency channels of the IEEE 802.15.3c standard (58.32 to 64.8 GHz) is fully integrated in a 0.12-μm SiGe BiCMOS process. It consists of an up-conversion core followed by a 1:16 power distribution tree, 16 phase-shifting front-ends, and a digital control unit. The TX core is a two-step sliding-IF up-conversion chain with frequency synthesizer that features 40 dB of gain programmability, I/Q balance and LO leakage correction, and a modulator for 802.15.3c common-mode signaling. The tradeoffs involved in the implementation of a 1:16 power distribution network are analyzed and a hybrid passive/active distribution tree architecture is introduced. Each of the 16 front-ends consists of a balanced passive phase shifter and a variable-gain, 3-stage PA that features oP1dB programmability through the bias control of the its final stage. All of the chip features are digitally controllable and individual memory arrays are integrated at each front-end to enable fast beam steering through a high-speed parallel interface. The IC occupies 44 mm and is fully characterized on wafer. The TX delivers 9 to 13.5 dBm oPidB per element at 60.48 GHz with a total power consumption of 3.8 to 6.2 W. Each element attains a phase-shift range >360° with an amplitude variation <;±1 dB across phase settings and adjacent elements. Measurement results from a packaged IC in an antenna chamber are also presented including the demonstration of spatial power combining up to +40 dBm EIRP and 16-element radiation patterns.

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications

Graphene is a relatively new material with unique properties that holds promise for electronic applications. Since 2004, when the first graphene samples were intentionally fabricated, the worldwide research activities on graphene have literally exploded. Apart from physicists, also device engineers became interested in the new material and soon the prospects of graphene in electronics have been considered. For the most part, the early discussions on the potential of graphene had a prevailing positive mood, mainly based on the high carrier mobilities observed in this material. This has repeatedly led to very optimistic assessments of the potential of graphene transistors and to an underestimation of their problems. In this paper, we discuss the properties of graphene relevant for electronic applications, examine its advantages and problems, and summarize the state of the art of graphene transistors.

Graphene Transistors: Status, Prospects, and Problems

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

Record RF performance of 45-nm SOI CMOS Technology

Sub-1V supplies limit the output voltage swing and saturated output power of an amplifier integrated in deep-submicron CMOS technology. Aside from absolute output power, power-added efficiency (PAE), stability and gain are also important power-amplifier (PA) design considerations. High reverse isolation between output and input is necessary to mitigate the effects of antenna mismatch, limit unwanted interference between circuit blocks on-chip and to promote stability. Efficiency of the PA is also paramount for portable consumer electronic applications operating from a battery, such as short-range Gb/s communication SoCs operating in the unlicensed bands around 60GHz. Aside from the 60GHz band, long-range collision-avoidance radar for automobiles (77/79GHz), and radio imaging (94GHz) are also potential applications for CMOS at mm-wave frequencies [1–4].

A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBM's large volume 200mm fabrication line. The technology features 300 GHz f T and 360 GHz f MAX high performance SiGe HBTs, 135 GHz f T and 2.5V BV CEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

Integrated circuit having pairs of parallel complementary FinFETs

A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yields 5.7 dB of MSG at 150 GHz. Measurement shows the amplifier exhibits 8.2 dB of gain, 6.3 dBm of Psat, 1.5 dBm of PidB and 27 GHz of 3 dB bandwidth, while consuming 25.5 mW at 1.1 V. The dummy-prefilled microstrip line exhibits QTL ? 12 up to 200 GHz.

John J. Pekarik

Papers

Record RF performance of 45-nm SOI CMOS Technology

A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

Integrated circuit having pairs of parallel complementary FinFETs

A 150 GHz Amplifier With 8 dB Gain and $+$ 6 dBm $P_{\rm sat}$ in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines