Jong Beom Park

Abstract: This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today's CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows.

Abstract: In this paper, we present 3-D-DATE, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90–16 nm, across a broader range of emerging transistor devices and through-silicon vias. This paper improves upon previous studies by providing detailed process models all the way down to the 16-nm technology node and incorporating DRAMs implemented with emerging gate transistor devices. Finally, we validate the model against both several commodity planar and 3-D DRAMs, from 80- to 30-nm process nodes, with the following metrics: energy with a mean error of 5%–1% and a standard deviation up to 9.8%, speed with a mean error of 13%–27%, and a standard deviation up to 24% and area within 3%–1% and a standard a standard deviation up to 4.2%.

Abstract: 3D technologies offer significant potential to improve raw performance and performance per unit power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create more sophisticated solutions that promise further increases in power/performance beyond those attributable to memory interfaces alone. These include heterogeneous integration and exploitation of the high amounts of interconnect available to provide for customization. Challenges include the creation of physical standards and the design of sophisticated static and dynamic thermal management methods.

Abstract: System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack.

Abstract: In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

Abstract: 3D technologies offer significant potential to improve total performance and performance per unit of power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create sophisticated logic on logic solutions that promise further increases in performance/power beyond those attributable to memory interfaces alone. These include heterogeneous integration for computing and exploitation of the high amounts of 3D interconnect available to reduce total interconnect power. Challenges include access for prototype quantities and the design of sophisticated static and dynamic thermal management methods and technologies, as well as test.

Abstract: Three dimensional integration technologies offer significant potential to improve performance, performance per unit power and integration density. However, increased power density and thermal resistances leading to higher on-chip temperature is imposing several implementation challenges and restricting widespread adaptation of this technology. This necessitates the need for CAD flows and tools facilitating early thermal evaluation of possible 3D design choices and thermal management techniques. This paper presents a CAD flow and associated framework called Pathfinder3D, which facilitates physically-aware system-level thermal simulation of 3DICs. Usage of Pathfinder3D is shown using a case study comparing thermal profiles of 2D and three 3D implementations of a quadcore chip multiprocessor.

Abstract: 3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.