Showing papers by "Jongwook Jeon published in 2017"

Development of Organic Semiconductors Based on Quinacridone Derivatives for Organic Field-Effect Transistors: High-Voltage Logic Circuit Applications

Abstract: Poly[quinacridone-alt-quaterthiophene] (PQCQT) was synthesized, using a Suzuki coupling reaction, to investigate the potential of quinacridone derivatives as organic semiconductors in organic fieldeffect transistors (OFETs) and circuits. A PQCQT film annealed at 150 °C yielded quite high field-effect performances, including a hole mobility of $2.0 \times 10^{-2}$ cm2/(Vs). In addition, to confirm the feasibility of using PQCQT in high-voltage circuit applications, electrical behaviors of PQCQT-based OFETs were described by extracting the model parameters of the industry standard compact Berkeley short-channel IGFET model. From the developed OFET model parameter set, we successfully evaluated the circuit operation of a p-type organic inverter with a frequency of 45.5 kHz in an 80 V supply condition.

Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Abstract: The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.

Repurposing compact discs as master molds to fabricate high-performance organic nanowire field-effect transistors

Abstract: Organic field-effect transistors (OFETs) have been developed over the past few decades due to their potential applications in future electronics such as wearable and foldable electronics. As the electrical performance of OFETs has improved, patterning organic semiconducting crystals has become a key issue for their commercialization. However, conventional soft lithographic techniques have required the use of expensive processes to fabricate high-resolution master molds. In this study, we demonstrated a cost-effective method to prepare nanopatterned master molds for the fabrication of high-performance nanowire OFETs. We repurposed commercially available compact discs (CDs) as master molds because they already have linear nanopatterns on their surface. Flexible nanopatterned templates were replicated from the CDs using UV-imprint lithography. Subsequently, 6,13-bis-(triisopropylsilylethynyl) pentacene nanowires (NWs) were grown from the templates using a capillary force-assisted lithographic technique. The NW-based OFETs showed a high average field-effect mobility of 2.04 cm2 V−1 s−1. This result was attributed to the high crystallinity of the NWs and to their crystal orientation favorable for charge transport.

Accurate BEOL statistical modeling methodology with circuit-level multi-layer process variations

Abstract: As technology scales down, the impact of BEOL (Back-end of Line) interconnect resistance (R) and capacitance (C) on speed and power of digital circuits have been ever- increasing. Furthermore, in 3-D structured transistors, such as FinFETs and Nano-wire FETs, the parasitic R & C of MOL (Middle of Line) have larger impact on performance and power of the products. Hence, analysis of impact on variations of BEOL and MOL on parasitic component change is necessary. The conventional interconnect corner model uses extreme BEOL variations. However, the possibility of such extreme conditions occurring is stochastically very rare. Therefore, tightened corner models were proposed in order to reduce excessiveness in corner simulations. But this tightened corner models still have excessive ranges because each layer is statistically analyzed separately. In this study, we propose a circuit-level multi-layers aware BEOL corner (CMBC) based on Monte Carlo (MC) simulation of ring-oscillator circuits. This modeling methodology takes into account of both MOL process variations and multi-BEOL layers. As a result, the proposed corner model has a tighter distribution ranges of R & C. Therefore the proposed model allows circuit designers to reduce unnecessary efforts.

Circuit design method and simulation method based on process variation caused by aging

Abstract: A circuit design method includes extracting aging information of each of multiple devices from a netlist including one or more devices and a model library including information associated with a process variation. An arithmetic operation is performed using the information associated with the process variation and the aging information to calculate a deviation of the process variation of each device caused by aging. A netlist and/or a model library is extracted in which the calculated deviation is reflected.

A sub-0.5 V operating RF low noise amplifier using tunneling-FET

Abstract: 60 nm tunneling FET (TFET) based low noise amplifier (LNA) with a sub-0.5 V supply voltage for 2.4 GHz WSN application has been evaluated systematically from device level up to circuit level design. With the help of TFET's unique property of high subthreshold swing, it shows that substantial increase of gain performance was confirmed compared to that of conventional LNA using 60 nm bulk MOSFET at ultra-low voltage (ULV) condition. From the simulation study, TFET LNA at 0.4 V operating voltage has the gain of 15.1 dB and noise figure 50 of 3.5 dB while dissipating DC power consumption of 0.41 mW.

Circuit design method, and circuit simulation method, and simulation system based on computer

Abstract: The invention provides a circuit design method, and a circuit simulation method, and a simulation system based on a computer. The circuit design method includes extracting aging information of each of multiple devices from a netlist including one or more devices and a model library including information associated with a process variation. An arithmetic operation is performed using the information associated with the process variation and the aging information to calculate a deviation of the process variation of each device caused by aging. A netlist and/or a model library is extracted in which the calculated deviation is reflected.

Circuit design method and simulation method based on random telegraph signal noise

Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.

Design optimization of RF low noise amplifier in twin‐well CMOS process

Abstract: This article presents an optimization technique aiming to improve gain and noise performances simultaneously, through the design of a cost-effective low noise amplifier (LNA) in a mixed-signal CMOS process without an RF triple-well option. To alleviate the inherent body-effect within a twin-well MOS transistor, we applied a transmission-line based source degeneration inductor Ls instead of a conventional spiral in the RF amplifier. In our design, without additional DC-power payment, the gain and noise figures (NF50) improved by 26% and 7.1%, respectively, when compared to the conventional spiral. The proposed LNA was implemented in a 0.18 µm 1-poly 6-metal mixed-signal CMOS process, and achieved a 13.1 dB gain and 2.72 dB noise figure while dissipating 8.76 mA from a 1.4 V supply.

Simulation method, circuit design method and schematic tool

Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected. In addition, a circuit design method and a schematic tool are also provided.

Semiconductor device including a fin pattern

Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.

Noise figure improvement by controlling wiring effects in RF low noise amplifiers

Abstract: In this letter, we evaluate the noise figure (NF) improvement that results from controlling the parasitic gate resistance of a radio-frequency (RF) low noise amplifier (LNA). By optimizing the number of gate contacts and wiring modifications in our fabricated device, the customized layout exhibited an approximately 25% reduction in the gate electrode resistance (Relect) when compared to a reference device provided by the foundry. The fabricated LNA, which used a customized layout in a 0.18 μm standard CMOS process, improved the NF by almost 6% without affecting the Si area and DC power consumption, and exhibited a NF of 2.57 dB, gain of 11.6 dB, DC power dissipation of 4.0 mW, and return loss at both the input and output of more than 10 dB. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1405–1407, 2017