K.T. San

TL;DR: The suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed and some technological challenges will be addressed.

TL;DR: SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration and NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS.

TL;DR: In this article, the performance of nMOS and pMOS tall triple gate (MUGFET) devices with fin widths down to 20 nm fabricated for the first time on super critical strained Si on insulator (SC-SSOI).

TL;DR: An investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design with impact on cell area and scalability is presented and trade-offs are explored.

TL;DR: In this article, the authors investigate technological solutions both at the process integration and layout levels to alleviate the parasitics that offset the performance gain that can be achieved through gate length scaling.