Showing papers by "Kees Goossens published in 2019"

Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs

Abstract: Wireless sensor networks (WSNs) are considered as a promising solution in intravehicle networking to reduce wiring and production costs. This application requires reliable and real-time data delivery, while the network is very dense. The time-slotted channel hopping (TSCH) mode of the IEEE 802.15.4 standard provides a reliable solution for low-power networks through guaranteed medium access and channel diversity. However, satisfying the stringent requirements of in-vehicle networks is challenging and demands for special consideration in network formation and TSCH scheduling. This paper targets convergecast in dense in-vehicle WSNs, in which all nodes can potentially directly reach the sink node. A cross-layer low-latency topology management and TSCH scheduling (LLTT) technique is proposed that provides a very high timeslot utilization for the TSCH schedule and minimizes communication latency. It first picks a topology for the network that increases the potential of parallel TSCH communications. Then, by using an optimized graph isomorphism algorithm, it extracts a proper match in the physical connectivity graph of the network for the selected topology. This network topology is used by a lightweight TSCH schedule generator to provide low data delivery latency. Two techniques, namely grouped retransmission and periodic aggregation, are exploited to increase the performance of the TSCH communications. The experimental results show that LLTT reduces the end-to-end communication latency compared to other approaches, while keeping the communications reliable by using dedicated links and grouped retransmissions.

Defect-Location Identification for Cell-Aware Test

Abstract: Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the amount of test escapes compared to conventional automatic test pattern generation (ATPG). Our CAT flow consists of three steps: (1) defect-location identification (DLI), (2) defect characterization based on detailed analog simulation of the cells, and (3) cell-aware automatic test pattern generation (ATPG). This paper focuses on Step 1, as quality and cost are determined by the set of cell-internal defect locations considered in the remainder of the flow. Based on technology inputs from the user and a parasitic extraction (PEX) run that analyzes the cell layouts, we derive a set of open defects on and short defects between both transistor terminals and intra-cell interconnects. The full set of defect locations is stored for later use during failure analysis. Through dedicated DLI algorithms, we identify a compact subset of defect locations for defect characterization and ATPG, in which we include only one representative defect location for each set of equivalent defects locations. For Cadence’s GPDK045 library, the compact subset contains only 2.8% of the full set of defect locations and reduces the time required for defect characterization with the same ratio.

Component-Level ASIL Decomposition for Automotive Architectures

Abstract: The Automotive industry is evolving towards a more electronics-assisted driving and self-driving functionality. The addition of complex subsystems has a great impact on the current vehicle architectures, leading to safety concerns. In this work we present a technique that follows the ISO 26262: Road Vehicles - Functional Safety standard to introduce redundancy in the architecture by using ASIL decomposition, and perform a safety analysis of the modelled system. A three-layer model is used to describe the application, the resources, and the physical space of the vehicle. In this paper we introduce novel model transformations to replicate parts of the application following ASIL decomposition rules. Finally, we perform a cost analysis and a probabilistic fault tree analysis on the architecture, making a comparison between different possible solutions. The advantages of these techniques, such as traceability and scalability, are shown by modelling and analysing the lateral control application of a real truck platooning system.

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices

Abstract: Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the number of test escapes compared to conventional automatic test pattern generation (ATPG) approaches that cover cell-internal defects only serendipitously. CAT consists of two steps, viz. (1) library characterization and (2) cell-aware ATPG. Defect detection matrices (DDMs) are used as the interface between both CAT steps; they record which cell-internal defects are detected by which cell-level test patterns. This paper proposes two algorithms that manipulate DDMs to optimize cell-aware ATPG results with respect to fault coverage, test pattern count, and compute time. Algorithm 1 identifies don't-care bits in cell patterns, such that the ATPG tool can exploit these during cell-to-chip expansion to increase fault coverage and reduce test-pattern count. Algorithm 2 selects, at cell level, a subset of preferential patterns that jointly provides maximal fault coverage at a minimized stimulus care-bit sum. To keep the ATPG compute time under control, we run cell-aware ATPG with the preferential patterns first, and a second ATPG run with the remaining patterns only if necessary. Selecting the preferential patterns maps onto a well-known N Phard problem, for which we derive an innovative heuristic that outperforms solutions in the literature. Experimental results on twelve circuits show average reductions of 43% of non-covered faults and 10% in chip-pattern count.

A Scalable and Fast Model for Performance Analysis of IEEE 802.15.4 TSCH Networks

Abstract: The IEEE 802.15.4 Time-Slotted Channel Hopping (TSCH) protocol has received considerable attention in many industrial applications. However, analytical models for fast performance estimation of TSCH-based networks by considering the interaction between Medium Access Control (MAC) and Physical (PHY) layers is an open problem. In this paper, we propose a stochastic model for performance analysis of TSCH-based networks including dedicated and shared links with non-ideal wireless link properties. The proposed model is scalable and is able to evaluate the MAC performance of a large-scale network quickly. The developed model is verified by simulations and real-world experiments. The results confirm the accuracy of the proposed model for large-scale networks with orders of magnitude faster execution compared to the existing model in the literature. This confirms the speed and scalability of the model, which makes it a perfect tool for network design and optimization.

Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms

Abstract: We compare three platform-aware feedback control design flows that are tailored for a composable and predictable Time Division Multiplexing (TDM)-based execution platform. The platform allows for independent execution of multiple applications. Using the precise timing knowledge of the platform execution, we accurately characterise the execution of the control application (i.e., sensing, computing, and actuating operations) to design efficient feedback controllers with high control performance in terms of settling time. The design flows are derived for Single-Rate (SR) and Multi-Rate (MR) sampling schemes. We show the applicability of the design flows based on two design considerations and their trade-off: control performance and resource utilisation. The design flows are validated by means of MATLAB and Hardware-in-the-Loop (HIL) experiments for a motion control application.

Delay-based Design of Feedforward Tracking Control for Predictable Embedded Platforms

Abstract: This paper presents a design technique for feedforward tracking control targeting predictable embedded platforms. An embedded control implementation experiences sensor-to-actuator delay which in turn changes the location of the system zeros. In this work, we show that such delay changes the number of unstable zeros which influences the tracking performance. We propose a zero loci analysis with respect to the delay and identify delay regions which potentially improve tracking performance. We utilize the analysis results to improve tracking performance of implementations targeting modern predictable embedded architectures where the delay can be precisely regulated. We validate our results by simulation and hardware-in-the-loop (HIL) implementation considering a real-life motion system.

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring

Abstract: Tracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slack monitoring techniques intend to measure worst-case static slack, i.e. the slack of longest timing path. In sharp contrast to the conventional techniques, we propose a novel technique that is based on dynamic excitation of in-situ delay monitors, i.e. dynamic excitation of the timing paths that are monitored. As the delays degrade, the path delays increase and the monitors are excited more frequently. With the proposed technique, a fine-grained signature of the delay degradation is extracted from the excitation rate of monitors.

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention

Abstract: In this paper, a timing speculation technique with low-overhead in situ delay monitors placed along critical paths is presented. The proposed insertion of monitors enables timing error prevention within the same clock cycle. Compared to other techniques, the design cost per monitor in our technique is low because no additional gates for the guard banding, inspection window generation, and short path extension are required. We benchmarked our approach on an ARM Cortex M0. The insertion strategy reduces the number of monitors by up to $\sim 23\times $ , power by $\sim 5.5\times $ , and area by $\sim 2.8\times $ compared to the traditional in situ monitoring techniques that insert monitors at the flip-flops. The timing error correction uses a global clock stretching unit to prevent errors within one cycle. With the proposed error prevention technique, ~22% more delay variation is tolerated with a negligible energy overhead of less than ~1%.

Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms

Abstract: From model-based design to implementation on an embedded platform requires target-specific code generation, compilation, and execution. Processor-in-the-loop (PIL) simulation is an intermediate step meant for detailed testing and debugging in the development process. This paper presents a PIL simulation framework targeting multi-core FPGA-based embedded platforms. The presented framework allows for a fully automated process of performing PIL simulations on an FPGA-based embedded platform - CompSOC - starting from a Simulink model. The framework includes two PIL configurations - one configuration executes only the controller code on the target platform while other configuration executes both the controller and the plant code on the target platform. It considers scheduling of multiple applications and interference-free execution on the target platform under the PIL configurations. Further, the framework allows for logging various measurements of parameters such as execution time, memory usage and so on in the PIL configurations which can be used for testing and debugging purposes.