K
Kota V. R. M. Murali
Researcher at IBM
Publications - 59
Citations - 1272
Kota V. R. M. Murali is an academic researcher from IBM. The author has contributed to research in topics: Field-effect transistor & Transistor. The author has an hindex of 19, co-authored 59 publications receiving 1116 citations. Previous affiliations of Kota V. R. M. Murali include Massachusetts Institute of Technology & Indian Institute of Technology Kharagpur.
Papers
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Journal ArticleDOI
Effect of Band-to-Band Tunneling on Junctionless Transistors
Suresh Gundapaneni,Mohit Bajaj,Rajan K. Pandey,Kota V. R. M. Murali,Swaroop Ganguly,Anil Kottantharayil +5 more
TL;DR: In this paper, the authors evaluate the impact of band-to-band tunneling on the characteristics of n-channel junctionless transistors (JLTs) and present guidelines to optimize the device for high on-tooff current ratio.
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A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance
TL;DR: In this paper, a modified structure of tunnel field effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET), has been proposed, which has a large tunneling cross-sectional area with a tunneling distance of ~2 nm.
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Probing decoherence with electromagnetically induced transparency in superconductive quantum circuits.
TL;DR: It is discussed how a superconductive analog to electromagnetically induced transparency can be used to establish macroscopic coherence in such systems and, thereby, be utilized as a sensitive probe of decoherence.
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Quantum-information processing by nuclear magnetic resonance: Experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system
Kota V. R. M. Murali,Neeraj Sinha,T. S. Mahesh,Malcolm H. Levitt,K. V. Ramanathan,Anil Kumar +5 more
TL;DR: In this paper, the use of a spin-7/2 as a three-qubit system and experimentally implementing the half-adder and subtractor operations is described. But labeling of quantum states of system can be suitably chosen to increase the efficiency of a computational task.
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CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET
Kaushik Nayak,Mohit Bajaj,Aniruddha Konar,Philip J. Oldiges,Kenji Natori,Hiroshi Iwai,Kota V. R. M. Murali,Valipe Ramgopal Rao +7 more
TL;DR: In this article, a detailed 3D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies.