An intermediate substrate includes a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor layer. The handle substrate may be a metal or metal alloy substrate, such as a molybdenum or molybdenum alloy substrate, while the thin layer may be a sapphire layer. A method of making the intermediate substrate includes forming a weak interface in the source substrate, bonding the source substrate to the handle substrate, and exfoliating the thin layer from the source substrate such that the thin layer remains bonded to the handle substrate.

Bonded intermediate substrate and method of making same

Elastic effects on surface physics

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Three dimensional device integration method and integrated device

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Method for low temperature bonding and bonded structure

We report an optical link on silicon using micrometer-scale ring-resonator enhanced silicon modulators and waveguide-integrated germanium photodetectors. We show 3 Gbps operation of the link with 0.5 V modulator voltage swing and 1.0 V detector bias. The total energy consumption for such a link is estimated to be ~120 fJ/bit. Such a compact and low power monolithic link is an essential step towards large-scale on-chip optical interconnects for future microprocessors.

Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors.

Semiconductor wafer bonding has increasingly become a technology of choice for materials integration in microelectronics, optoelectronics, and microelectromechanical systems. The present overview concentrates on some basic issues associated with wafer bonding such as the reactions at the bonding interface during hydrophobic and hydrophilic wafer bonding, as well as during ultrahigh vacuum bonding. Mechanisms of hydrogen-implantation induced layer splitting (“smart-cut” and “smarter-cut” approaches) are also considered. Finally, recent developments in the area of so-called “compliant universal substrates” based on twist wafer bonding are discussed.

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Fundamental issues in wafer bonding

Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to be within a temperature window that is specific for each material. The experimentally determined temperature windows for some semiconductors and single crystalline oxides will be given.

Transfer of semiconductor and oxide films by wafer bonding and layer cutting

Hydrogen-implantation induced blistering and layer transfer of LaAlO3 and sapphire

"Wafer bonding" refers to the phenomenon that mirror-polished, flat and clean surfaces of almost any material, when brought into contact at room temperature, are locally attracted to each other by van-der-Waals forces and adhere or bond to each other. Semiconductor wafer bonding has increasingly become a technology of choice for materials integration in microelectronics, optoelectronics, and microelectromechanical systems (MEMS). The presentation gives an overview of the fundamentals of wafer bonding and discusses the different approaches used for silicon wafers (usually bonded at room temperature in air) and for III-V compound wafers (often bonded at elevated temperatures around 500/spl deg/C in hydrogen). A critical assessment is given of so-called "universal compliant substrates" fabricated by twist wafer bonding, which are supposed to allow heteroepitaxial growth of materials with large misfit without the generation of threading dislocations.

Wafer bonding: a flexible approach to materials integration

The present paper proposes a simple method which may be able to provide true single-crystal films of complex oxides on large substrates including semiconductors like silicon or gallium arsenide. The method describes a layer transfer process using layer splitting by hydrogen implantation and direct wafer bonding (DWB) to obtain single-crystal oxide films on different substrates. Alternatively, a fabrication process of ferroelectric-semiconductor heterostructures based on direct wafer bonding and layer transfer is also described. This process is an alternative method to the direct deposition of oxides films (ferroelectric, high-k) on silicon and allows fabrication of metal oxide-silicon heterostructures with an interface having a good structural quality as well as a low trap density.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400182090

L.-J. Huang

Papers

Fundamental issues in wafer bonding

Transfer of semiconductor and oxide films by wafer bonding and layer cutting

Hydrogen-implantation induced blistering and layer transfer of LaAlO3 and sapphire

Wafer bonding: a flexible approach to materials integration

Wafer Bonding Involving Complex Oxides