The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

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Electronic Transport In Mesoscopic Systems

Journal of Applied physics,Vol.33 : 1962年に発表されたレオロジー関連の論文

Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ ${{\mu }}$ m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

Solid-state electronics

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=10V) Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT) Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response

Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

Ultrathin Ni silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi2 layers were grown at temperatures > 450°C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi2 is about one order of magnitude lower than that of a NiSi layer on both As- and B-doped SOI and SSOI.

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been fabricated showing reduction of the switching loss by more than 90% compared to a silicon IGBT/diode half bridge.

Lars Knoll

Papers

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

Robust 3.3kV silicon carbide MOSFETs with surge and short circuit capability