Proceedings ArticleDOI
Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling
Lars Knoll,Qing-Tai Zhao,A. Nichau,S. Richter,G. V. Luong,Stefan Trellenkamp,A. Schafer,Luca Selmi,Konstantin Bourdelle,S. Mantl +9 more
TLDR
In this paper, a gate all around strained Si (sSi) nanowire array TFET array with high ION (64μA/μm at VDD=10V) was presented.Abstract:
We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=10V) Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT) Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time responseread more
Citations
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Journal ArticleDOI
Demonstration of L-Shaped Tunnel Field-Effect Transistors
TL;DR: In this article, an L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time.
Journal ArticleDOI
A Review of Sharp-Switching Devices for Ultra-Low Power Applications
TL;DR: In this article, a review of CMOS-compatible devices capable of switching more abruptly than MOSFETs, and discuss their merits and limitations is presented. But the authors do not consider the effect of channel materials and geometries.
Journal ArticleDOI
InAs/Si Hetero-Junction Nanotube Tunnel Transistors
TL;DR: Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement.
Journal ArticleDOI
Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells
Sebastiano Strangio,Pierpaolo Palestri,David Esseni,Luca Selmi,Felice Crupi,S. Richter,Qing-Tai Zhao,Siegfried Mantl +7 more
TL;DR: In this article, the authors used mixed device-circuit simulations to predict the performance of 6T static RAM (SRAM) cells implemented with tunnel-FETs (TFETs).
Journal ArticleDOI
Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors.
TL;DR: This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon andgermanium Nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.
References
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors
Lars Knoll,Qing-Tai Zhao,A. Nichau,Stefan Trellenkamp,S. Richter,A. Schafer,David Esseni,Luca Selmi,Konstantin Bourdelle,S. Mantl +9 more
TL;DR: In this article, the first uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field effect transistors (TFETs) are fabricated.
Journal ArticleDOI
CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$ -mV/decade Subthreshold Swing
TL;DR: In this paper, a vertical-silicon-nanowire-based p-type tunneling field effect transistor (TFET) using CMOS-compatible process flow was presented, achieving subthreshold swing (SS) of 30 mV/decade averaged over a decade of drain current and an Ion/Ioff ratio of >; 105.
Journal ArticleDOI
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs
Anne Vandooren,Daniele Leonelli,Rita Rooyackers,Andriy Hikavyy,Katia Devriendt,Marc Demand,Roger Loo,Guido Groeseneken,Cedric Huyghebaert +8 more
TL;DR: In this article, the authors report on the integration of vertical nTunnel FETs (TFETs) with SiGe hetero-junction and analyzes the presence of trap-assisted tunneling impacting the device behavior.
Journal ArticleDOI
Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric
Kirsten E. Moselund,Mikael Björk,Heinz Schmid,H. Ghoneim,Siegfried Karg,Emanuel Lörtscher,Walter Riess,Heike Riel +7 more
TL;DR: In this article, p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile were fabricated with three different gate dielectrics, SiO2, Al2O3, and HfO2.
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Tunnel field-effect transistors as energy-efficient electronic switches
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