A mean-field phase diagram for conformationally symmetric diblock melts using the standard Gaussian polymer model is presented. Our calculation, which traverses the weak- to strong-segregation regimes, is free of traditional approximations. Regions of stability are determined for disordered (DIS) melts and for ordered structures including lamellae (L), hexagonally packed cylinders (H), body-centered cubic spheres (QIm3m), close-packed spheres (CPS), and the bicontinuous cubic network with Ia3d symmetry (QIa3d). The CPS phase exists in narrow regions along the order−disorder transition for χN ≥ 17.67. Results suggest that the QIa3d phase is not stable above χN ∼ 60. Along the L/QIa3d phase boundaries, a hexagonally perforated lamellar (HPL) phase is found to be nearly stable. Our results for the bicontinuous Pn3m cubic (QPn3m) phase, known as the OBDD, indicate that it is an unstable structure in diblock melts. Earlier approximation schemes used to examine mean-field behavior are reviewed, and compa...

Unifying Weak- and Strong-Segregation Block Copolymer Theories

An overview of through-silicon-via technology and manufacturing challenges

The red shift and the broadening of the Raman signal from microcrystalline silicon films is described in terms of a relaxation in the q-vector selection rule for the excitation of the Raman active optical phonons. The relationship between width and shift calculated from the known dispersion relation in c-Si is in good agreement with available data. An increase in the decay rate of the optical phonons predicted on the basis of the same model is confirmed experimentally.

The one phonon raman spectrum in microcrystalline silicon

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI has been electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10- and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 100-nm-thick Ta layer exhibit no change after annealing up to 60 min at 300 °C. However, the C-t curves of the trench capacitors with 10-nm-thick Ta layer were severely degraded even after the initial annealing for 5 min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 × 1012 /cm 2 and the size is ~2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 106 P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5 min at 300°C. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. However, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min. Based on the C-t evaluation results, we developed high reliable and fine-size of 5-μm diameter backside Cu TSV to achieve high reliability and high-end 3-D LSIs.

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs

The behavior of Cu contamination at the backside surface of a thinned wafer in a three-dimensional (3D) LSI was electrically evaluated by capacitance–time (C–t) analysis In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 50 µm and 100 µm thickness, respectively For an accelerated Cu diffusion test, a thin Cu layer was deposited at the back surface as a contamination source Cu atoms were artificially diffused into the substrate by annealing at 200 °C and 300 °C for various times in nitrogen ambient The C–t curves of a MOS capacitor formed on a 100 µm thickness substrate were degraded even after annealing at 200 °C It means that Cu atoms diffuse into the active region and reach the Si–SiO2 interface during relatively low-temperature annealing By increasing time and temperature, the transient time tf is more seriously decreased The C–t curves of the MOS capacitor formed on the Si substrate of 50 µm thickness were more seriously degraded even after the initial annealing at 200 °C for 5 min These results indicate that the Cu contamination issue becomes more severe in a thinner Si substrateThis study shows that C–t analysis is a highly promising method to electrically evaluate the influence of Cu contamination on device reliability in the 3D LSI

http://iopscience.iop.org/article/10.1088/0268-1242/26/2/025007/pdf

M. Koyanagi

Papers

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs

Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement