Showing papers by "Matteo Sonza Reorda published in 2002"

New Techniques for Speeding-Up Fault-Injection Campaigns

Abstract: Fault-tolerant circuits are currently required in several major application sectors, and a new generation of CAD tools is required to automate the insertion and validation of fault-tolerant mechanisms. This paper outlines the characteristics of a new fault-injection platform and its evaluation in a real industrial environment. The fault-injection platform is mainly used for assessing the correctness and effectiveness of the fault tolerance mechanisms implemented within ASIC and FPGA designs. The platform works on register transfer-level VHDL descriptions which are then synthesized, and is based on commercial tools for VHDL parsing and simulation. It also details techniques devised and implemented within the platform to speed-up fault-injection campaigns. Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.

High-level and hierarchical test sequence generation

Abstract: Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

Abstract: In this paper, two low-cost solutions devoted to provide processor-based systems with error-detection capabilities are compared. The effects of single event upsets (SEUs) and single event transients (SETs) are studied through simulation-based fault injection. The error-detection capabilities of a hardware-implemented solution based on parity code are compared with those of a software-implemented solution based on source-level code modification. Radiation testing experiments confirmed results obtained by simulation.

A new approach to software-implemented fault tolerance

Abstract: A new approach for providing fault detection and correction capabilities by using software techniques only is described. The approach is suitable for developing safety-critical applications exploiting unhardened commercial-off-the-shelf processor-based architectures. Data and code duplications are exploited to detect and correct transient faults affecting the processor data segment, while control flow instruction duplication is used for detecting and correcting faults affecting the code segment. Results coming from extensive fault injection campaigns showed the effectiveness and the limitations of the method.

Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs

Abstract: Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new fault injection environment, which offers an alternative to radiation testing for evaluating the effects of charged particles on the configuration memory of SRAM-based FPGA devices. This paper describes the fault injection environment and reports preliminary results gathered on some benchmark circuits.

A new functional fault model for FPGA application-oriented testing

Abstract: The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates that the faults affecting the bit cells of the look-up tables (LUTs) are not redundant, although they store constant values. We demonstrate that these faults cannot be neglected and that the fault model corresponding to modifying the content of each LUT memory cell must be considered in order to cover the full range of possible faults. In order to evaluate the fault coverage of the proposed fault model, a set of circuits mapped on a Xilinx Virtex 300 FPGA have been considered. Test sequences generated by a gate-level commercial ATPG and an academic RT-level one have been fault simulated on these benchmark circuits. The obtained figures show that a high percentage of faults affecting the LUT bit cells are undetected, thus suggesting that suitable ATPG algorithms adopting the new fault model are required.

Fault list compaction through static timing analysis for efficient fault injection experiments

Abstract: With the adoption of deep sub-micron technologies, faults modeled as single event transients (SETS) on combinational gates are becoming an issue, but efficient and accurate techniques for assessing their impact on VLSI designs are still missing. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tackling SET effects. By resorting to static timing analysis, the approach is able to prune the set of possible faults and to identify a superset of the ones that may produce effects on the circuit outputs. Experimental results are reported on standard benchmarks assessing the effectiveness of the proposed approach.

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

Abstract: This paper proposes a new solution for the diagnosis of faults in embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuitry added to the BIST selecting the failure data, and the ATE test program to schedule the data extraction flow. Testing is possible through a standard IEEE 1149.1 TAP, and allows the access to multiple cores with a P1500 compliant solution. The approach aims at implementing a low-cost solution to diagnose embedded RAMs with the goal of minimizing the ATE costs and the time required to extract the diagnostic information. In our approach, the ATE drives the diagnostic scheme and is dedicated to the classification of faults, only, allowing adopting low-cost equipment. The proposed solution allows a scalable extraction of test data, whose amount is proportional to the available testing time. In order to accelerate the fault classification, image processing techniques have been applied The Hough transform has been adopted to analyze the bitmap representing the faulty cells. Preliminary experimental results show the advantages of the proposed approach in terms of time required to complete a diagnostic process.

Report on benchmark identification and planning of experiments to be performed

Abstract: The document describes the benchmarks we have identified as test cases to be used during the COTEST project. Being the project focused both on the high-level generation of suitable test/validation vectors and on the high-level insertion of design for testability structures, we identified benchmarks of different characteristics and complexity. The document also outlines the experiments that we intend to perform during the project.

Evolutionary Techniques for Minimizing Test Signals Application Time

Abstract: Reducing production-test application time is a key problem for modern industries. Several different hardware solutions have been proposed in the literature to ease such process. However, each hardware architecture must be coupled with an effective test signals generation algorithm. This paper propose an evolutionary approach for minimizing the application time of a test set by opportunely extending it and exploiting a new hardware architecture, named interleaved scan. The peculiarities of the problem suggest the use of a slightly modified genetic algorithm with concurrent populations. Experimental results show the effectiveness of the approach against the traditional ones.

BUILT-IN SELF TEST OF SEQUENTIAL CIRCUITS A New Evolutionary Paradigm for Cultivating Cellular Automata

Abstract: This chapter describes an innovative Built-In Self Test architecture based on cellular automata. The architecture is an enhancement of standard Circular Self­ Test Path, and increases stuck-at fault coverage while maintaining all advantages, such as low timing intrusiveness, easy integration into design flow, at-speed testing. Cellular automaton rules are devised using the Selfish Gene algorithm, a new evolutionary algorithm based on an unorthodox view of the Darwinian theory, where the basic units of selection are genes rather than individuals. Experimental results show the effectiveness of the approach and the efficacy of the Selfish Gene algorithm.