Synthesis of Wafer-Scale Graphene with Chemical Vapor Deposition for Electronic Device Applications

FDSOI devices are prominently used in low power circuits and high frequency domains due to their superior RF and analog performance, thanks to back-bias capability and relatively ease of transistor design over FinFETs and planar bulk transistors. BSIM-IMG is the industry standard compact model for simulating FDSOI devices. In this work, we will discuss recent enhancements made in the BSIM-IMG model for accurate modeling of the FDSOI transistors. The back gate inversion is more physically modeled in the latest BSIM-IMG model. We will present a new 1/f noise model, which is validated with the experimental data. Improved output conductance, mobility and gate current models are also discussed. All the enhancements are done in such a way that benchmark RF figure of merit are met.

BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion

Author(s): Lin, Yen-Kai | Advisor(s): Hu, Chenming | Abstract: Compact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis. TFET has a gated p-i-n diode structure, where the current relies on direct band-to-band tunneling in source/channel junction. Such tunneling mechanism breaks the tradition limitation of MOSFET turn-ON characteristics called the Boltzmann tyranny. The improvements in power consumption and delay of circuits are thus the emphasis and attention of device community, where the need of TFET compact model is fulfilled with the developed model in this work. NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET. The short channel effect, ferroelectric variability, and spacer optimization design are the focus in this thesis. The compact model of NCFET is improved to be more predictive for ferroelectric properties with verification against TCAD simulations. Monte-Carlo method is carried out in FE variability study, where the main finding is that the dielectric phase is critical but fortunately is theoretically possible to be absent. The spacer design reveals that further engineering the capacitance matching via parasitic capacitance is the key solution for future technology nodes.In addition to transistor compact models and physics, the memory device - spin-transfer-torque magnetic tunnel junction (STT-MTJ) is also presented. The resistances and critical currents are derived from the Landau-Lifshitz-Gilbert (LLG) equation and modeled analytically. The RC sub-circuit is found to describe the dynamic switching behavior of MTJ due to the precession and thermal fluctuation. The proposed MTJ compact model has been validated with silicon data from the industry and is capable of simulating a memory circuit with previously mentioned BSIM models.

Compact Modeling of Advanced CMOS and Emerging Devices for Circuit Simulation

This chapter describes the drain current model in BSIM-IMG. The core drain current model discussed in Chapter 2, Core Model for Independent Multigate metal oxide field effect transistor (MOSFETs), describes an ideal long channel device. However, actual devices have several physical phenomena (also known as real device effects) which affect the terminal current. This chapter describes these important phenomena and their modeling in BSIM-IMG model. This chapter is divided into various sections. Each section discusses specific device phenomena, details how the phenomena is analytically modeled, and introduces the model parameters associated with the phenomena.

Channel Current Model With Real Device Effects in BSIM-IMG

Planar MOSFETs are widely recognized as key drivers of the semiconductor industry. This chapter presents analytical models and useful charts for IC design using the most advanced planar MOSFET technological nodes. After a brief review of the progress in MOSFET architectures, the state-of-the-art UTBB FDSOI technology advantages are compiled, and some important designer needs are reminded. The main physical ingredients involved in the MOSFET strong inversion operation are reviewed and generalized to the UTBB FDSOI transistors with a particular focus on the back-gate voltage impact. For better insight into the weak inversion and moderate inversion regimes, both the low-frequency gm/ID FoM and the high-frequency ym/ID FoM are presented. A modeling of the UTBB FDSOI MOSFET is proposed for low-frequency and high-frequency operations and compared to measurements considering distributed effects in both the gate and the channel. The results show excellent agreement across all regimes of operation including very low bias conditions and up to 110 GHz. Finally, an LNA circuit first-cut sizing procedure using presented charts is proposed for an expected operation at 35 GHz. 

Planar MOSFETs and Their Application to IC Design

Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.

Michael Harter

Papers

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs